eda实验如何实现60进制计数器七段数码管的显示

实验四 七段数码管显示电路一、实验目的实现十六进制计数显示。二、硬件需求EDA/SOPC实验箱一台。三、实验原理七段数码管分共阳极与共阴极两种。共阳极数码管其工作特点是，当笔段电极接低电平，公共阳极接高电平时，相应笔段可以发光。共阴极数码管则与之相反，它是将发光二极管的阴极短接后作为公共阴极，当驱动信号为高电平、公共阴极接低电平时，才能发光。图2-13为共阳极数码管和共阴极数码管的内部结构图。图2-13 共阳极数码管和共阴极数码管的内部结构图用七段数码管除了可以显示0～9的阿拉伯数字外，还可以显示一些英语字母。下表是常见的字母与7段显示关系（共阴极数码管）。

段字母 a b c d e f g

A 0 0 0 1 0 0 0

B 1 1 0 0 0 0 0

C 0 1 1 0 0 0 1

D 1 0 0 0 0 1 0

E 0 1 1 0 0 0 0

F 1 0 0 0 1 1 1

H 0 1 1 0 1 1 1

四、实验内容编写一个0～F轮换显示的电路（注意：选用实验箱中的共阳数码管DP1A，FPGA上P25引脚连接50MHz时钟。实验时为了便于观察，要将50MHz时钟经过分频得到1Hz时钟）。五、实验步骤（1）实验程序LIBRARY IEEEUSE IEEE.std_logic_1164.allUSE IEEE.std_logic_unsigned.allENTITY exp2 ISGENERIC(n:INTEGER :=6)port(clk: IN std_logicled: OUT std_logic_vector(6 DOWNTO 0))END exp2ARCHITECTURE example OF exp2 ISSIGNAL sel:INTEGER RANGE 0 TO n-1 :=0SIGNAL f_out:std_logicSIGNAL count:INTEGER RANGE 0 TO 15 :=0

BEGINPROCESS(clk)BEGINIF clk'event and clk='1' THENIF sel>n-2 THEN sel<=0ELSEIF sel>=n/2 THENf_out<='1'ELSEf_out<='0'END IFsel<=sel+1END IFEND IFEND PROCESSPROCESS(f_out)BEGINIF f_out'event and f_out='1' THENIF count<=15 THENcount<=count+1ELSEcount<=0END IFEND IFEND PROCESSPROCESS(count)BEGINCASE count ISWHEN 0 =>led <="0000001"WHEN 1 =>led <="1001111"WHEN 2 =>led <="0010010"WHEN 3 =>led <="0000110"WHEN 4 =>led <="1001100"WHEN 5 =>led <="0100100"WHEN 6 =>led <="0100000"WHEN 7 =>led <="0001111"WHEN 8 =>led <="0000000"WHEN 9 =>led <="0000100"WHEN 10 =>led <="1110111"WHEN 11 =>led <="0011111"WHEN 12 =>led <="1001110"WHEN 13 =>led <="0111101"WHEN 14 =>led <="1001111"WHEN 15 =>led <="0111000"

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可编程逻辑器件实验EDA-七段数码管显示电路

实验四 七段数码管显示电路

一、实验目的

实现十六进制计数显示。

二、硬件需求

EDA/SOPC实验箱一台。

三、实验原理

七段数码管分共阳极与共阴极两种。共阳极数码管其工作特点是，当笔段电极接低电平，公共阳极接高电平时，相应笔段可以发光。共阴极数码管则与之相反，它是将发光二极管的阴极短接后作为公共阴极，当驱动信号为高电平、公共阴极接低电平时，才能发光。图2-13为共阳极数码管和共阴极数码管的内部结构图

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

ENTITY DECODE3_8 IS

PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0)

EN : IN STD_LOGIC

XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0))

END DECODE3_8

ARCHITECTURE ONE OF DECODE3_8 IS

BEGIN

PROCESS (DIN, EN)

BEGIN

IF EN = ‘1’ THEN

IF DIN = “111” THEN XOUT <= “11111110”

ELSIF DIN = “110” THEN XOUT <= “11111101”

ELSIF DIN = “101” THEN XOUT <= “11111011”

ELSIF DIN = “100” THEN XOUT <= “11110111”

ELSIF DIN = “011” THEN XOUT <= “11101111”

ELSIF DIN = “010” THEN XOUT <= “11011111”

ELSIF DIN = “001” THEN XOUT <= “10111111”

ELSE XOUT <= “11111011”

END IF

END PROCESS

END ONE

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_unsigned.all

entity angel is

port(clk:in std_logic

clr:in std_logic

q: out std_logic_vector(7 downto 0))

end angel

architecture one of angel is

begin

process(clk,clr)

variable cqi:std_logic_vector(7 downto 0)

variable s:std_logic :='0'--控制加减的标志

variable e:std_logic :='0'--控制幅度增减的标志

variable a:integer range 0 to 127--控制左边幅度的标志

variable b:integer range 255 downto 0--控制右边幅度的标志

begin

if clr='1' then cqi:="00000000"s:='0'e:='0'a:=0b:=255--end if

elsif clk'event and clk='1' then

case s is

when '0' =>if cqi<b then cqi:=cqi+1end if

if cqi=b then s:='1'

if a<127 and e='0' then a:=a+1else a:=a-1e:='1'

end if

end if

when '1' =>if cqi>a then cqi:=cqi-1end if

if cqi=a then s:='0'

if b>128 and e='0' then b:=b-1

else b:=b+1end if

if b=255 then cqi:="00000000"s:='0'e:='0'a:=0end if

end if

end case

end if

q<=cqi

end process

end one

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