VHDL一个小程序的错误

不要将信号的边沿检测搞成这么多。写成下面这样试试看：

if clk'event and clk='1' then

if et='0' then

case state is

when "00" =>count := 0stop := 0

when "01" =>count := 2stop := 0

when "10" =>count := 5stop := 0

when others =>stop := 1

end case

else if count=0 then count := 9

else count := count-1

end if

end if

end if

vhdl分顺序执行语句和并行执行语句 有的书按分类介绍的if，case等语句 你可以看看

process到end process之间的语句属于顺序执行语句 就是从上到下，顺序执行

process之外的程序都是并行执行语句 就是同时执行

begin

process(clock)

if rising_edge(clock) then--顺序执行语句，你如果把process删了使用if语句的话，编 译器会报错

clk<=not clk--顺序执行语句

end if--顺序执行语句

end process

clkout<=clk--并行执行语句

end

VHDL语言编写一个七段译码电路（共阳极）

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

ENTITY DecL7S IS

PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0)

LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) )

END

ARCHITECTURE one OF DecL7S IS

BEGIN

PROCESS( A )

BEGIN

CASE A(3 DOWNTO 0) IS

WHEN "0000" => LED7S <= "0111111" -- X“3F”0

WHEN "0001" => LED7S <= "0000110" -- X“06”1

WHEN "0010" => LED7S <= "1011011" -- X“5B”2

WHEN "0011" => LED7S <= "1001111" -- X“4F”3

WHEN "0100" => LED7S <= "1100110" -- X“66”4

WHEN "0101" => LED7S <= "1101101" -- X“6D”5

WHEN "0110" => LED7S <= "1111101" -- X“7D”6

WHEN "0111" => LED7S <= "0000111" -- X“07”7

WHEN "1000" => LED7S <= "1111111" -- X“7F”8

WHEN "1001" => LED7S <= "1101111" -- X“6F”9

WHEN "1010" => LED7S <= "1110111" -- X“77”10

WHEN "1011" => LED7S <= "1111100" -- X“7C”11

WHEN "1100" => LED7S <= "0111001" -- X“39”12

WHEN "1101" => LED7S <= "1011110" -- X“5E”13

WHEN "1110" => LED7S <= "1111001" -- X“79”14

WHEN "1111" => LED7S <= "1110001" -- X“71”15

WHEN OTHERS => NULL

END CASE

END PROCESS

END

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