vivado中的一个bug，重金求解

输入正确代码解决：

initialbegin#0key1=0key2=0key3=0#10000000key1=1key2=0key3=0#1000000key1=0key2=0key3=0#10000000

key1=0key2=1key3=0#1000000key1=0key2=0key3=0#10000000key1=0key2=0key3=1#1000000key1=0key2=0key3=0end。

扩展资料：

vivado中的一个bug出现的原因：

“All-Programmable”器件不只是涵盖可编程逻辑设计，还涉及到可编程系统集成，要在更少的芯片上集成越来越多的系统功能。为了构建上述系统，我们会面临一系列全新的集成和实现设计生产力瓶颈，这是必须要解决的问题：

集成瓶颈，集成C 语言算法和RTL 级IP，混合DSP、嵌入式、连接功能、逻辑领域，模块和“系统”验证，设计和IP 重用，实现瓶颈，层次化芯片布局规划与分区，多领域和多晶片物理优化，多变量“设计”和“时序”收敛的冲突，设计后期发生的ECO及变更引起的连锁反应

FPGA分配引脚有几种方法： 1，在你的VHDL里面用约束把管脚直接绑定到某个管脚 2，开发系统里可以编辑一个约束文件，把所有的管脚约束都房子这个文件里面； 3，开发系统里还提供一个图形化的工具，你可以拉动你的IO脚到某个PAD。

[DRC NSTD-1] Unspecified I/O Standard: 4 out of 134 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPIO_LED_0[3:0].

[DRC UCIO-1] Unconstrained Logical Port: 4 out of 134 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPIO_LED_0[3:0].

pin planning error原因是   GPIO_LED_0[3:0]  和xdc文件上的名称不一致  xdc是GPIO_LED[3:0] 。注意观察bd文件中的引脚名称和xdc文件是否一样，或者打开implementation----->layout----->io管脚来观看是否引脚对的。或参考 https://www.eefocus.com/otod3r/blog/14-04/302799_38ddf.html 试试

2.

[BD 41-1356] Address block </math_ip_0/S_AXI/reg0>is not mapped into </processing_system7_0/Data>.。。。。。。。。。。。。。。

错误原因：地址分配有问题，点击其中一个小按钮自动分配下地址就行了

---