半导体，集成电路原理设计

1、集电极电位不相同的NPN晶体管必须放在不同的隔离区，而集电极电位相同的NPN晶体管可以放在同一个隔离区内。2、多数电阻原则上都可以放在同一个隔离区内，只要保证它们之间实现电隔离。3、基区扩散电阻两端电位不高于NPN晶体管集电极电位时，可与NPN晶体管同放一个隔离区内；基区扩散电阻两端电位不高于横向PNP晶体管基极电位时，可与横向PNP晶体管同放一个隔离区内。

根据这几条比对电路图。这个电路实际上是个反相器，或者说是交流转直流的一个东西。VI高电平时输出低电平，VI低电平时，或者为负时输出高电平。

根据那几条，可以看出Q5、Q6为一个区，其他为一个区。

仅是个人观点，对隔离区不是很了解

RF CMOS / SiGe HBT / GaAs HBT　

In the last years RF CMOS power amplifiers have been introduced. SiGe Bipolar power amplifiers are available since a couple of year already. But they have not established in volume supply in the hand-set industry as already mentioned. TriQuint also has been engaged in this technology over several years with the development and release of CDMA power amplifier, in SiGe and GaAs. This development team now is exclusively working on GaAs HBT based devices. The main reasons are performance cost. The long lasting dispute between Silicon and GaAs with arguments like: Silicon is more mature and predictable, can be produced at lower cost, and integrating new functions on chip is easier than in GaAs. In detail these are no longer true for today's challenging applications. GaAs processes have matured and cost disadvantages have been overcome by reaching volumes that have driven down substrate prices tremedously. Additionally GaAs has performance features that cannot always be metched by Silicon chip. Larger chip sizes have severe disadvantages because the die gets more expensive and secondly and even more important it has cost impact on the module and hampers the shrinkage path for future products. Chip cost for a SiGe chip with comparable performance and function are higher compared to a GaAs HBT die although the wafer cost still is lower, but the required die size is larger. SiGe RF power performance under high linearity requirements in high band for CDMA is not competitive to GaAs HBT. In a CDMA high band example the SiGe die was 2.5x the sizes of a GaAs solution resulted in a 15% lower cost for the full module.

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