关于VHDL中ALU里的移位运算和乘法运算？

例如 5的时候

when "1001" =>

if(B(2 downto 0) = "000") then

Reg3 <= Reg1

else

Reg3 <= Reg1((7-CONV_INTEGER(B)) downto 0) &Reg1(7 downto (8-CONV_INTEGER(B)))

endif

tmp不用了 直接删掉

还有shift的时候B只用3bit就能覆盖了

我没有编译 如果编译有问题继续问我

use ieee.std_logic_1164.all

use ieee.std_logic_signed.all

entity alu is

port (a,b:in std_logic_vector(3 downto 0)

c, d , e, f: out std_logic_vector(3 downto 0))

end alu

architecture behav of alu is

begin

c <= a + b

d <= a - b

e <= a and b

f <= a or b

end behav

备注：Quartus II 8.0下 编译及仿真通过。