LIBRARY ieee
USE ieee.std_logic_1164.all
ENTITY lamp1 IS
PORT( rst,start,clk: IN STD_LOGIC
sound_in: IN STD_LOGIC
sel: IN STD_LOGIC_VECTOR(1 DOWNTO 0)
sound_out: OUT STD_LOGIC
led: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
)
END lamp1
ARCHITECTURE bd OF lamp1 IS
TYPE state IS(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16)
SIGNAL style:state
BEGIN
pr1:PROCESS(rst,start,sel,clk)
BEGIN
IF rst='0' THEN style<=s0
ELSIF clk'event AND clk='1' THEN
IF start='1' THEN
CASE style IS
WHEN s0=>style<=s1
WHEN s1=>style<=s2
WHEN s2=>style<=s3
WHEN s3=>style<=s4
WHEN s4=>style<=s5
WHEN s5=>style<=s6
WHEN s6=>族耐 style<=s7
WHEN s7=>style<=s8
WHEN s8=>style<=s9
WHEN s9=>style<=s10
WHEN s10=>style<=s11
WHEN s11=>style<=s12
WHEN s12=>style<=s13
WHEN s13=>style<=s14
WHEN s14=>style<=s15
WHEN s15=>style<=s16
WHEN s16=>style<=s1
END CASE
END IF
END IF
IF(clk='1') THEN sound_out<=sound_in
ELSE sound_out<='0'
END IF
END PROCESS
pr2:PROCESS(sel,style)
BEGIN
IF sel="00" THEN
CASE style IS
WHEN s0=>led<="0000000000000000"
WHEN s1=>led<="兆裂春1000000000000001"
WHEN s2=>led<源昌="0010000000000100"
WHEN s3=>led<="0000100000010000"
WHEN s4=>led<="0000001001000000"
WHEN s5=>led<="0000000110000000"
WHEN s6=>led<="0000001111000000"
WHEN s7=>led<="0000011111100000"
WHEN s8=>led<="0000111111110000"
WHEN s9=>led<="0001111111111000"
WHEN s10=>led<="0011111111111100"
WHEN s11=>led<="0111111111111110"
WHEN s12=>led<="1111111111111111"
WHEN s13=>led<="1111111001111111"
WHEN s14=>led<="1111100000011111"
WHEN s15=>led<="1110000000000111"
WHEN s16=>led<="1000000000000001"
END CASE
ELSIF sel="01" THEN
CASE style IS
WHEN s0=>led<="0000000000000000"
WHEN s1=>led<="0000000000000011"
WHEN s2=>led<="0000000000001111"
WHEN s3=>led<="0000000000111111"
WHEN s4=>led<="0000000011111111"
WHEN s5=>led<="0000001111111111"
WHEN s6=>led<="0000111111111111"
WHEN s7=>led<="0011111111111111"
WHEN s8=>led<="1111111111111111"
WHEN s9=>led<="1111111111111100"
WHEN s10=>led<="1111111111110000"
WHEN s11=>led<="1111111111000000"
WHEN s12=>led<="1111111100000000"
WHEN s13=>led<="1111110000000000"
WHEN s14=>led<="1111000000000000"
WHEN s15=>led<="1100000000000000"
WHEN s16=>led<="0000000000000000"
END CASE
ELSIF sel="10" THEN
CASE style IS
WHEN s0=>led<="0000000000000000"
WHEN s1=>led<="1110000000000000"
WHEN s2=>led<="0011100000000000"
WHEN s3=>led<="0000111000000000"
WHEN s4=>led<="0000001110000000"
WHEN s5=>led<="0000000011100000"
WHEN s6=>led<="0000000000111000"
WHEN s7=>led<="0000000000001110"
WHEN s8=>led<="0000000000000011"
WHEN s9=>led<="0000000000001110"
WHEN s10=>led<="0000000000111000"
WHEN s11=>led<="0000000011100000"
WHEN s12=>led<="0000001110000000"
WHEN s13=>led<="0000111000000000"
WHEN s14=>led<="0011100000000000"
WHEN s15=>led<="1110000000000000"
WHEN s16=>led<="1000000000000000"
END CASE
ELSIF sel="11" THEN
CASE style IS
WHEN s0=>led<="0000000000000000"
WHEN s1=>led<="1111000000000001"
WHEN s2=>led<="0111100000000010"
WHEN s3=>led<="0011110000000100"
WHEN s4=>led<="0001111000001000"
WHEN s5=>led<="0000111100010000"
WHEN s6=>led<="0000011110100000"
WHEN s7=>led<="0000001111000000"
WHEN s8=>led<="0000011110010000"
WHEN s9=>led<="0000111110000100"
WHEN s10=>led<="0001111000000001"
WHEN s11=>led<="0011110000000100"
WHEN s12=>led<="0111100000010000"
WHEN s13=>led<="1111000001000000"
WHEN s14=>led<="0111100100000000"
WHEN s15=>led<="0011111000000000"
WHEN s16=>led<="0111100000010000"
END CASE
END IF
END PROCESS
END bd
实验四 七段数码管显示电路一、实验目的悉宏实现十六进制计数显示。二、硬件需求EDA/SOPC实验箱一台。三、实验原理七段数码管分共阳极与共阴极两种。共阳极数码管其工作特点是，当笔段电极接低电平，公共阳极接高电平时，相应笔段可以发光。共阴极数码管则与之相反，它是将发光二极管的阴极短接后作为公共阴极，当驱动信号为高电平、公共阴极接低电平时，才能发光。图2-13为共阳极数码管和共阴极陆陆困数码管的内部结构图。图2-13 共阳极数码管和共阴极数码管的内部结构图用七段数码管除了可以显示0～9的阿拉伯数字外，还可以显示一些英语字母。下表是常见的字母与7段显示关系（共阴极数码管）。段字母 a b c d e f g
A 0 0 0 1 0 0 0
B 1 1 0 0 0 0 0
C 0 1 1 0 0 0 1
D 1 0 0 0 0 1 0
E 0 1 1 0 0 0 0
F 1 0 0 0 1 1 1
H 0 1 1 0 1 1 1
四、实验内容编写一个0～F轮换显示的电路（注意：选用实验箱中的共阳数码管DP1A，FPGA上P25引早念脚连接50MHz时钟。实验时为了便于观察，要将50MHz时钟经过分频得到1Hz时钟）。五、实验步骤（1）实验程序LIBRARY IEEEUSE IEEE.std_logic_1164.allUSE IEEE.std_logic_unsigned.allENTITY exp2 ISGENERIC(n:INTEGER :=6)port(clk: IN std_logicled: OUT std_logic_vector(6 DOWNTO 0))END exp2ARCHITECTURE example OF exp2 ISSIGNAL sel:INTEGER RANGE 0 TO n-1 :=0SIGNAL f_out:std_logicSIGNAL count:INTEGER RANGE 0 TO 15 :=0
BEGINPROCESS(clk)BEGINIF clk'event and clk='1' THENIF sel>n-2 THEN sel<=0ELSEIF sel>=n/2 THENf_out<='1'ELSEf_out<='0'END IFsel<=sel+1END IFEND IFEND PROCESSPROCESS(f_out)BEGINIF f_out'event and f_out='1' THENIF count<=15 THENcount<=count+1ELSEcount<=0END IFEND IFEND PROCESSPROCESS(count)BEGINCASE count ISWHEN 0 =>led <="0000001"WHEN 1 =>led <="1001111"WHEN 2 =>led <="0010010"WHEN 3 =>led <="0000110"WHEN 4 =>led <="1001100"WHEN 5 =>led <="0100100"WHEN 6 =>led <="0100000"WHEN 7 =>led <="0001111"WHEN 8 =>led <="0000000"WHEN 9 =>led <="0000100"WHEN 10 =>led <="1110111"WHEN 11 =>led <="0011111"WHEN 12 =>led <="1001110"WHEN 13 =>led <="0111101"WHEN 14 =>led <="1001111"WHEN 15 =>led <="0111000"
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可编程逻辑器件实验EDA-七段数码管显示电路
实验四 七段数码管显示电路
一、实验目的
实现十六进制计数显示。
二、硬件需求
EDA/SOPC实验箱一台。
三、实验原理
七段数码管分共阳极与共阴极两种。共阳极数码管其工作特点是，当笔段电极接低电平，公共阳极接高电平时，相应笔段可以发光。共阴极数码管则与之相反，它是将发光二极管的阴极短接后作为公共阴极，当驱动信号为高电平、公共阴极接低电平时，才能发光。图2-13为共阳极数码管和共阴极数码管的内部结构图
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