怎样用verilog设计一个比较器

module compare_8(a,b,out)

input[7:0] a

input[7:0] b

output out

reg out

always @(a or b)

begin

if(a>b) out=1

else

out=0

end

endmodule

看看行不雀颂配樱档行，没编译过，应该顷指能用

module (

input [7:0] in1, in2, in3,

output [7:0] out1)

wire [7:0] w

assign w = in1 >in2 ? in2 : in1

assign out1 = w <弊激销租游铅碰 in3 ? w : in3

endmodule

刚给你写的，也没编迟陆译，不过应该没错，自码知顷己去调试吧

module count(clk,flag)

input clk

reg [7:0] i

output flag

reg flag

always @(posedge clk)

begin

if(i == 8'b1111_1111)

begin

i <= 8'b00000000

flag <= 1

end

else if(i == 8'b0000_0001)

begin

flag <= 0

i <猛简= i+1

end

else

i <= i+1

end

endmodule

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