input rst
input [7:0] data_in
output [7:0] data_out
reg [7:0] data
wire data_out
always @ (posedge clk or negedge rst)
if (~rst)
data <= data_in
else
data <= data<<1// 此处先移空塌高位核空,后低位; 如果先低后高改为:data <= data>>1
assign data_out = data[7]// 此处先移高位,后低位;改亏瞎 如果先低后高改为:data[0]
VHDL: Bidirectional Busdownload from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee
USE ieee.std_logic_1164.ALL
ENTITY bidir IS
PORT(
bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
oe, clk : IN STD_LOGIC
inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0))
END bidir
ARCHITECTURE cpld OF bidir IS
SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0) -- DFF that stores
-- value from input.
SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0) -- DFF that stores
BEGIN-- feedback value.
PROCESS(clk)
BEGIN
IF clk = '1'培橘 AND clk'镇闭EVENT THEN -- Creates the flipflops
a <= inp
outp <配旅团= b
END IF
END PROCESS
PROCESS (oe, bidir) -- Behavioral representation
BEGIN-- of tri-states.
IF( oe = '0') THEN
bidir <= "ZZZZZZZZ"
b <= bidir
ELSE
bidir <= a
b <= bidir
END IF
END PROCESS
END cpld
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