1、设计任务及要求：
设计任务：设计一台能显示时、分、秒的数字钟。具体要求如下：
由实验箱上的时钟信号经分频产生秒脉冲；
计时计数器用24进制计时电路；
可手动校时，能分别进行时、分的校正；
整点报时；
2 程序咐碧指代码及相应波形
Second1(秒计数 6进制和10进制)
Library ieee
Use ieee.std_logic_1164.all
Use ieee.std_logic_unsigned.all
Entity second1 is
Port( clks,clr:in std_logic
Secs,Secg: out std_logic_vector(3 downto 0)
cout1:out std_logic)
End second1
Architecture a of second1 is
Begin
Process(clks,clr)
variable ss,sg: std_logic_vector(3 downto 0)
variable co: std_logic
Begin
If clr='1' then ss:="0000"sg:="0000"
Elsif clks'event and clks='1' then
if ss="0101" and sg="1001" then ss:="0000"sg:="0000"co:='1'
elsif sg<"1001" then sg:=sg+1co:='0'
elsif sg="1001" then sg:="0000"ss:=ss+1co:='0'
end if
end if
cout1<=co
Secs<=ss
Secg<=sg
end process
End a
Min1（分计数衡配器 6进制和10进制 alm实现整点报时）
Library ieee
Use ieee.std_logic_1164.all
Use ieee.std_logic_unsigned.all
Entity min1 is
Port(clkm,clr:in std_logic
mins,ming:buffer std_logic_vector(3 downto 0)
enmin,alarm: out std_logic)
End
Architecture a of min1 is
Begin
Process(clkm,clr)
variable ms,mg :std_logic_vector(3 downto 0)
variable so,alm :std_logic
Begin
If clr='1' then ms:="0000"mg:="0000"
Elsif clkm'event and clkm='1' then
if ms="0101" and mg="1001" then ms:="慧巧0000"mg:="0000"so :='1'alm:='1'
elsif mg<"1001" then mg:=mg+1so :='0'alm:='0'
elsif mg="1001" then mg:="0000"ms:=ms+1so :='0'alm:='0'
end if
end if
alarm<=alm
enmin<= so
mins<=ms
ming<=mg
End process
End a
Hour1（时计数器 4进制与2进制）
Library ieee
Use ieee.std_logic_1164.all
Use ieee.std_logic_unsigned.all
Entity hour1 is
Port(clkh,clr:in std_logic
hours,hourg:out std_logic_vector(3 downto 0))
End
Architecture a of hour1 is
Begin
Process(clkh,clr)
variable hs,hg :std_logic_vector(3 downto 0)
Begin
If clr='1' then hs:="0000"hg:="0000"
Elsif clkh'event and clkh='1' then
if hs="0010"and hg="0011" then hs:="0000"hg:="0000"
elsif hg<"1001" then hg:=hg+1
elsif hg="1001" then hg:="0000"hs:=hs+1end if
end if
hours<=hs
hourg<=hg
End process
End
Madapt（校分）
Library ieee
Use ieee.std_logic_1164.all
Use ieee.std_logic_unsigned.all
Entity madapt is
Port(en,clk,secin,m1:in std_logic
minset:out std_logic)
End
Architecture a of madapt is
Begin
Process(en,m1)
Begin
if en='1' then
if m1='1' then minset<=clk
else minset<=secinend if
else minset<=secin
end if
End process
end
Hadapt (校时)
Library ieee
Use ieee.std_logic_1164.all
Use ieee.std_logic_unsigned.all
Entity hadapt is
Port(en,clk,minin,h1:in std_logic
hourset:out std_logic)
End
Architecture a of hadapt is
Begin
Process(en,h1)
Begin
if en='1' then
if h1='1' then hourset<=clk
else hourset<=mininend if
else hourset<=minin
end if
End process
end
Topclock（元件例化 顶层文件）
Library ieee
Use ieee.std_logic_1164.all
Use ieee.std_logic_arith.all
Use ieee.std_logic_unsigned.all
Entity topclock is
Port(clk,clr,en,m1,h1:in std_logic
alarm:out std_logic
secs,secg,mins,ming,hours,hourg:buffer std_logic_vector(3 downto 0))
End
Architecture one of topclock is
Component second1
Port( clks,clr:in std_logic
secs,secg: buffer std_logic_vector(3 downto 0)
cout1: out std_logic)
End Component
Component min1
Port(clkm,clr:in std_logic
mins,ming:buffer std_logic_vector(3 downto 0)
enmin,alarm: out std_logic)
End Component
Component hour1
Port(clkh,clr:in std_logic
hours,hourg:buffer std_logic_vector(3 downto 0))
End Component
Component madapt
Port(en,m1,clk,secin:in std_logic
minset:out std_logic)
End Component
Component hadapt
Port(en,h1,clk,minin:in std_logic
hourset:out std_logic)
End Component
signal a,b,c,d: std_logic
begin
u1:second1 port map(clr=>clr,
secs=>secs,secg=>secg,clks=>clk, cout1=>a)
u2:min1 port map(clr=>clr,alarm=>alarm,
mins=>mins,ming=>ming,clkm=>b,enmin=>c)
u3:hour1 port map(clr=>clr,
hours=>hours,hourg=>hourg,clkh=>d)
u4:madapt port map(en=>en,m1=>m1,clk=>clk,secin=>a,minset=>b)
u5:hadapt port map(en=>en,h1=>h1,clk=>clk,minin=>c,hourset=>d)
end
3 电路图
仿真自己去搞啦
支持PID控制，正困迅有功能块，去西门子官方网站下载PID文献，百度文库里也有，很详细，注意PID功能块的选用（一般用的举此比尺此较多的有连续响应PID和步进响应PID，还有温度控制PID，以及功能块引脚的作用就可以了。欢迎分享，转载请注明来源：内存溢出
微信扫一扫
支付宝扫一扫
评论列表（0条）