用verilog代码编写下面的程序

这就是誉老亩把ABC三个电台的启动信号变为输入，XY的启动信号为输出，列出真值表就行了吧。庆森

真值含皮表为：

a

b

c

x

y

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

module clk_div(clk,out1,out2)

input clk

output out1,out2

reg out1,out2

reg [31:0]cnt1,cnt2

always @(posedge clk)begin//50MHz分频计肢宽和数

if(cnt1<32'd24999999)

cnt1 <=cnt1 + 32'巧缓d1

else

cnt1 <=32'd0

end

always @(posedge clk)//分频历盯后的半周期反转

if(cnt1 == 0)

out1<=~out1

always @(posedge clk)begin//5MHz分频计数

if(cnt2<32'd4999999)

cnt2 <=cnt2 + 32'd1

else

cnt2 <=32'd0

end

always @(posedge clk)//20%占空比

if(cnt2 == 32'd999999)

out2<=0

else if(cnt2 == 32'd4999999)

out2<=1

endmodule

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