急救 用verilog HDL语言设计一个m序列的生成程序，您之前有有解决过相关问题。

我m序列代码赋值下来是，发现wire和x中间没有空格，这可能是导致你没有输出的原因祥中，个人建议你的代码这样写：

module prbs(clk,rst,m_out)

input clk,rst

output m_out

reg[7:0] reg_buf

reg x

always@(posedge clk or posedge rst)

if(!rst)

begin

reg_buf[7:0] <= 8'b1000_0000

x <= 1'帆友b1

end

else

begin

reg_buf[7:0] <态宴槐= {reg_buf[6:0],x}

x <= reg_buf[7]^reg_buf[3]^reg_buf[2]^reg_buf[1]

end

assign m_out = reg_buf[7]

endmodule

下面的代码我已经用modelsim仿真过了，没有悉烂型问题。睁猜

module count(out,clk,rst)//源程序

input clk,rst

output[3:0] out

reg[3:0] out

initial out=4'd0

always @(posedge clk or negedge rst)

begin

if(!rst) out=4'd0

else

begin

out=out+4'd1

if(out==4'd1||out==4'd6||out==4'd8) out=out+4'd1

if(out==4'd5) out=out+4'd2

end

end

endmodule

`timescale 1ns/1ns //测试历伏程序

`include "count.v"

module count_tp

reg clk,rst

wire[3:0] out

parameter DELY=100

count mycount(out,clk,rst)

always #(DELY/2) clk=~clk

initial

begin

clk=0rst=1

#(DELY*5) rst=0

#DELY rst=1

#(DELY*20) $finish

end

initial $monitor($time,,,"clk=%d rst=%d out=%d",clk,rst,out)

endmodule

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