Verilog HDL的数字秒表和电子时钟设计

在module paobiao中把执行条件srt=1，在module shizhong中樱姿带把执行条件srt=0

通过按键册氏消抖，当按键按一下是对外部srt=~srt执行一脊芦次。其他的计时很容易设计。

定义参数BaudGeneratorAccWidth = 16；

定睁圆义线网【16：0】BaudGeneratorInc=Baud左移16-4=12位+ClkFrequency右移5位))除(ClkFrequency右移4位)

定义reg【16：0】BaudGeneratorAcc；

always块悉扒塌：

时钟沿触发此轮

如果TxD_busy=1；

那么BaudGeneratorAcc 被赋予BaudGeneratorAcc[BaudGeneratorAccWidth-1:0]（BaudGeneratorAcc的0到15位） + BaudGeneratorInc；

定义wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]

end

直接verilog代码就可以了吧？

以前写的一个代码，供参考。

module clock(clk,rst,set, set_typ, set_data, yr, mon, dt, hr, min, sec,

alarm_en, alm_typ, alm_yr, alm_mon, alm_dt, alm_hr, alm_min, alm_sec, alarm_output)

input clk,rst,set

input [2:0] set_typ //

input [6:0] set_data//

output [6:0] yr, mon, dt, hr, min, sec

input alarm_en

input [2:0] alm_typ //

input [6:0] alm_yr, alm_mon, alm_dt, alm_hr, alm_min, alm_sec

output alarm_output

parameter C_FR= 32'd20_000_000-32'd1 //定义系统时钟20MHz

reg [31:0] fr_cnt

reg [3:0] sec_cnt

reg pp1s //秒脉冲

//==================================================

//fr_cnt

always@(posedge clk)//

if(!rst)

fr_cnt <= 32'b0

else if (fr_cnt >= C_FR)

fr_cnt <= 32'b0

else

fr_cnt <= fr_cnt + 1'b1

//pp1s

always@(posedge clk)//

if(!rst)

pp1s <= 1'b0

else if (fr_cnt == C_FR)

pp1s <= 1'b1

else

pp1s <= 1'b0

/源弊备//time counter

always@(posedge clk)

if(!rst)

begin

yr <= 7'b0

mon <= 7'b0

dt <= 7'b0

hr <= 7'b0

min <= 7'b0

sec <= 7'b0

end

else if (set)

begin

case (set_typ)

3'卜没b000: yr <= set_data

3'b001: mon <= set_data

3'b010: dt <= set_data

3'b011: hr <= set_data

3'b100: min <= set_data

3'b101: sec <= set_data

end

else if (pp1s)

begin

if (sec >= 7'd59)

sec <= 7'd0

else

sec <= sec + 1'b1

if (sec >= 7'd59)

begin

if (min >= 7'雹毁d59)

min <= 7'd0

else

min <= min + 1'b1

end

if (sec >= 7'd59 &&min >= 7'd59)

begin

if (hr >= 7'd23)

hr <= 7'd0

else

hr <= hr + 1'b1

end

///data,mon, year, 大月小月，闰年等，依此类推

//

end

//=================================

//alarm

always@(posedge clk)

if(!rst)

alarm_output <= 1'b0

else if (alarm_en)

case (alm_typ)

3'b000:

if (yr == alm_yr &&mon == alm_mon &&dt == alm_dt &&hr == alm_hr &&min == alm_min &&sec == alm_sec)

alarm_output <= 1'b1

else

alarm_output <= 1'b0

3'b001:

if (mon == alm_mon &&dt == alm_dt &&hr == alm_hr &&min == alm_min &&sec == alm_sec)

alarm_output <= 1'b1

else

alarm_output <= 1'b0

3'b010:

if (dt == alm_dt &&hr == alm_hr &&min == alm_min &&sec == alm_sec)

alarm_output <= 1'b1

else

alarm_output <= 1'b0

3'b011:

if (hr == alm_hr &&min == alm_min &&sec == alm_sec)

alarm_output <= 1'b1

else

alarm_output <= 1'b0

3'b100:

if (min == alm_min &&sec == alm_sec)

alarm_output <= 1'b1

else

alarm_output <= 1'b0

default

alarm_output <= 1'b0

endcase

endmodule

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