洗衣机简易程序verilog 计时模块修正

module altera(clk,washingtime,pause,mode,minute1,minute2,second1,second2,led)

input clk

input [4:0]washingtime

input pause

input mode

output [3:0]minute1

output [3:0]minute2

output [3:0]second1

output [3:0]second2

output [3:0]led

reg [4:0]thetime

reg [5:0]CLK

reg [3:0]minute1

reg [3:0]minute2

reg [3:0]second1

reg [3:0]second2

reg [3:0]led

reg MODE

initial

begin

CLK<=6'd0

led[0]<=1'd0//正转

led[1]<=1'd0//间歇

led[2]<=1'd0//反转

led[3]<=1'd0//暂停

thetime<=washingtime

MODE<=mode

end

always@(posedge clk)//七段数码管值陆扒

if(thetime!=4'b0000&&pause!=1'd0)//工作状态倒计时(不停止不暂停时)

begin

CLK <= (CLK == 6'd60) ? 6'd0 : (CLK + 6'd1)

second1=(6'd59-CLK)/4'd10

second2=(6'd59-CLK)%4'd10

minute1=thetime/4'd10

minute2=thetime%4'd10

if(CLK==6'd59)

begin thetime<=thetime-1'd1

minute1=thetime/4'd10

minute2=thetime%4'd10

end

else if(thetime==4'd0000)//停止

begin minute1<=4'b0000

minute2<=4'b0000

second1<=4'b0000

second2<=4'b0000

end

end

always@(posedge clk)//led灯的判断

begin

if(pause==1'd1)

begin led[0]<=1'd0led[1]<=1'd0led[2]<=1'd0led[3]<=1'd1end

if(MODE==1'd0)

begin

if(CLK==5'd20)

begin led[0]<=1'd1led[1]<=1'd0led[2]<=1'd0led[3]<=1'd0end

else if(CLK==5'd30)

begin led[0]<=1'd0led[1]<=1'd1led[2]<=1'd0led[3]<=1'd0end

else if(CLK==5'd50)

begin led[0]<=1'd0led[1]<=1'd0led[2]<=1'd1led[3]<=1'd0end

end

else if(MODE==1'd1)

begin

if(CLK==5'd25)

begin led[0]<=1'早陆昌d1led[1]<=1'd0led[2]<=1'd0led[3]<=1'd0end

else if(CLK==5'悉告d30)

begin led[0]<=1'd0led[1]<=1'd1led[2]<=1'd0led[3]<=1'd0end

else if(CLK==5'd50)

begin led[0]<=1'd0led[1]<=1'd0led[2]<=1'd1led[3]<=1'd0end

end

end

endmodule

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你在判断CLK的值时，用的<=不是用的==

这样的话判断语句就一直为真，跳不到else的情况

加入一个约束条件，当暂停按下的时候，保持当冲逗桥前时间数值保持不变指袭；若想实现多控制的秒表，当按下暂停键时，保存当前的时间值，散猛可以在后续结束计数时，逐一提取之前所保存的时间值。

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