谁知道vhdl的乘除法怎么实现？？？

VHDL的乘法是利用移位相加来实现的，具体网上有很多程序可慧简埋供前蚂参考，如http://wontuoba.blog.163.com/blog/static/13485835420091123111635857/

链接内是以乘法器设计的VHDL程序。

至于除法运算，一般是通过查找表来实现的，取除数的倒数进行乘法运算，然后再对除数与其倒数一一对应的做查找表运算。

另咐咐外网上一般还提供一些稍微简化的运算方法如DA算法什么的，你可以自行搜索获知。

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library ieee

use ieee.std_logic_1164.all

entity MULTI8X8 is

port(CLK: in std_logic

START:in std_logic

A:in std_logic_vector(7 downto 0)

B:in std_logic_vector(7 downto 0)

ARIEND:out std_logic

DOUT:out std_logic_vector(15 downto 0))

end MULTI8X8

architecture art of MULTI8X8 is

component ARICTL

port(CLK: in std_logicSTART: in std_logic

CLKOUT: out std_logicRSTALL:out std_logic

ARIEND: out std_logic)

end component

component andarith

port(abin: in std_logic

din: in std_logic_vector(7 downto 0)

dout: out std_logic_vector(7 downto 0))

end component

component ADDER8B

port ( A : in std_logic_vector(7 downto 0)

B : in std_logic_vector(7 downto 0)

cin: in std_logic

s : out std_logic_vector(7 downto 0)

cout: out std_logic)

end component

component SREG8B

port (CLK: in std_logic

LOAD: in std_logic

DIN: in std_logic_vector(7 downto 0)

QB: out std_logic)

end component

component REG16B

port(CLK: in std_logic

clr:IN STD_LOGIC

D: in std_logic_VECTOR(8 DOWNTO 0)

Q: out std_logic_vector (15 downto 0))

end component

signal GNDINT: std_logic

signal INTCLK: std_logic

signal RSTALL: std_logic

signal QB: std_logic

signal ANDSD: std_logic_vector(7 downto 0)

signal DTBIN: std_logic_vector(8 downto 0)

signal DTBOUT: std_logic_vector(15 downto 0)

begin

DOUT<=DTBOUT GNDINT<= '0'

U1:ARICTL port map(CLK=>CLK, START=>运慎纯START,

CLKOUT=>孝坦INTCLK, RSTALL=>旁咐RSTALL,

ARIEND=>ARIEND)

U2:SREG8B port map(CLK=>INTCLK, LOAD=>RSTALL,

DIN=>B, QB=>QB)

U3:ANDARITH port map(ABIN=>QB,DIN=>A,

DOUT=>ANDSD)

U4:ADDER8B port map(CIN=>GNDINT,

A=>DTBOUT(15 downto 8),B=>ANDSD,

S=>DTBIN(7 downto 0),COUT =>DTBIN(8))

U5:REG16B port map(CLK =>INTCLK,CLR=>RSTALL,

D=>DTBIN, Q=>DTBOUT)

end art

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