在verilog数字系统中，有哪几种系统时钟

一、 各输入、输出信号引脚说明：CLK：时钟信号RST：系统复位信号，低电平有效。时钟复位后为：00 00 00。EN：暂停信号，低电平有效，按下该键，数字时钟暂停。S1：调节小时信号，低电平有效。每按下一次，小时增加一个小时。S2：调节分钟信号，低电平有效。每按下一次，分钟增加一个分钟。skp：输出到扬声器，在每个小时的59分50秒到0分10秒之间将会产生报警声音。HOURH,HOURL,MINH,MINL,SECH,SECL：分别对应小时、分钟、秒钟的十位和个位。 二、 Verilog HDL编写的数字时钟程序：module clock(CLK,RST,EN,S1,S2,spk,HOURH,HOURL,MINH,MINL,SECH,SECL)input CLK,RST,EN,S1,S2output spkoutput[3:0] HOURH,HOURL,MINH,MINL,SECH,SECLreg spkreg[3:0] SECL,SECH,MINL,MINH,HOURL,HOURH always @(posedge CLK or negedge RST) if(!RST) begin SECL<=0SECH<=0MINL<=0MINH<=0HOURL<=0HOURH<=0end //系统复位 else if(EN) //EN为低电平时时钟暂停 begin if(!S1) //调节小时 begin if(HOURL==9) begin HOURL<=0HOURH<=HOURH+1end else beginif(HOURH==2&&HOURL==3) begin HOURL<=0HOURH<=0endelse HOURL<=HOURL+1 end end else if(!S2) //调节分钟 begin if(MINL==9) beginMINL<=0if(MINH==5) MINH<=0else MINH<=MINH+1 end else MINL<=MINL+1 end else if(SECL==9) //时钟正常跳动状态 begin SECL<=0 if(SECH==5) beginSECH<=0if(MINL==9)begin MINL<=0 if(MINH==5) begin MINH<=0 if(HOURL==9) begin HOURL<=0HOURH<=HOURH+1end else if(HOURH==2&&HOURL==3)begin HOURL<=0HOURH<=0end else HOURL<=HOURL+1 end else MINH<=MINH+1endelse MINL<=MINL+1 end else SECH<=SECH+1 end else SECL<=SECL+1 end else begin HOURH<=HOURH HOURL<=HOURL MINH<=MINH MINL<=MINL SECH<=SECH SECL<=SECL end always @(posedge CLK) //产生报警声音模块 begin if(MINH==5&&MINL==9&&SECH==5) begin spk<=CLKend else if(MINH==0&&MINL==0&&SECH==0) spk<=CLK else spk<=0 endendmodule

定义参数BaudGeneratorAccWidth = 16；

定义线网【16：0】BaudGeneratorInc=Baud左移16-4=12位+ClkFrequency右移5位))除(ClkFrequency右移4位)

定义reg【16：0】BaudGeneratorAcc；

always块：

时钟沿触发

如果TxD_busy=1；

那么BaudGeneratorAcc 被赋予BaudGeneratorAcc[BaudGeneratorAccWidth-1:0]（BaudGeneratorAcc的0到15位） + BaudGeneratorInc；

定义wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]

end

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