use ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
--------------------------------------------------------------------
entity digital is
port( Clk : in std_logic --时钟输入
Rst : in std_logic --复位输入
S1,S2 : in std_logic --时间调节输入
led : out std_logic_vector(3 downto 0) --整点输报时输出
spk : out std_logic
Display : out std_logic_vector(6 downto 0) --七段码管显示输出
SEG_SEL : buffer std_logic_vector(2 downto 0) --七段码管扫描驱动
)
end digital
--------------------------------------------------------------------
architecture behave of digital is
signal Disp_Temp : integer range 0 to 15
signal Disp_Decode : std_logic_vector(6 downto 0)
signal SEC1,SEC10: integer range 0 to 9
signal MIN1,MIN10: integer range 0 to 9
signal HOUR1,HOUR10 : integer range 0 to 9
signal Clk1kHz: std_logic--数码管扫描时钟
signal Clk1Hz: std_logic--时钟计时时钟
signal led_count : std_logic_vector(2 downto 0)
signal led_display : std_logic_vector(3 downto 0)
signal spkcout: std_logic
begin
PROCESS(clk) --产生1hz信号
variable cnt : INTEGER RANGE 0 TO 49999999--产生1Hz时钟的分频计数器
BEGIN
IF clk='1' AND clk'event THEN
IF cnt=49999999 THEN cnt:=0
ELSE
IF cnt<25000000 THEN clk1hz<='1'
ELSE clk1hz<='0'
END IF
cnt:=cnt+1
END IF
END IF
end process
PROCESS(clk) --产生1hz信号
variable cnt1 : INTEGER RANGE 0 TO 49999--产生1KHz时钟的分频计数器
BEGIN
IF clk='1' AND clk'event THEN
IF cnt1=49999 THEN cnt1:=0
ELSE
IF cnt1<25000 THEN clk1khz<='1'
ELSE clk1khz<='0'
END IF
cnt1:=cnt1+1
END IF
END IF
end process
process(Clk1Hz,Rst)
begin
if(Rst='0') then--系统复位
SEC1<=0
SEC10<=0
MIN1<=0
MIN10<=0
HOUR1<=0
HOUR10<=0
elsif(Clk1Hz'event and Clk1Hz='1') then--正常运行
if(S1='0') then --调节小时
if(HOUR1=9) then
HOUR1<=0
HOUR10<=HOUR10+1
elsif(HOUR10=2 and HOUR1=3) then
HOUR1<=0
HOUR10<=0
else
HOUR1<=HOUR1+1
end if
elsif(S2='0') then --调节分钟
if(MIN1=9) then
MIN1<=0
if(MIN10=5) then
MIN10<=0
else
MIN10<=MIN10+1
end if
else
MIN1<=MIN1+1
end if
elsif(SEC1=9) then
SEC1<=0
if(SEC10=5) then
SEC10<=0
if(MIN1=9) then
MIN1<=0
if(MIN10=5) then
MIN10<=0
if(HOUR1=9) then
HOUR1<=0
HOUR10<=HOUR10+1
elsif(HOUR10=2 and HOUR1=3) then
HOUR1<=0
HOUR10<=0
else
HOUR1<=HOUR1+1
end if
else
MIN10<=MIN10+1
end if
else
MIN1<=MIN1+1
end if
else
SEC10<=SEC10+1
end if
else
SEC1<=SEC1+1
end if
end if
end process
process(Clk)--整点报时
begin
if(Clk1hz'event and Clk1hz='1') then
if(MIN10=5 and MIN1=9 and SEC10=5 and sec1>3) then--在59分55秒开始提示
led_Count<=led_Count+1spkcout<=not spkcout
else
led_count<="000"
spkcout<='0'
end if
spk<=spkcout
end if
end process
process(led_count)--整点报时LED灯的闪烁
begin
case (led_count) is
when "000"=>led_display<="0000"
when "001"=>led_display<="1111"
when "010"=>led_display<="0111"
when "011"=>led_display<="0011"
when "100"=>led_display<="0001"
when "101"=>led_display<="1111"
when others=>led_display<="0000"
end case
led<=led_display
end process
process(SEG_SEL)
begin
case (SEG_SEL+1) is
when "111"=>Disp_Temp<=HOUR10
when "110"=>Disp_Temp<=HOUR1
when "101"=>Disp_Temp<=10
when "100"=>Disp_Temp<=MIN10
when "011"=>Disp_Temp<=MIN1
when "010"=>Disp_Temp<=10
when "001"=>Disp_Temp<=SEC10
when "000"=>Disp_Temp<=SEC1
end case
end process
process(Clk1khz)
begin
if(Clk1khz'event and Clk1khz='1') then--扫描累加
SEG_SEL<=SEG_SEL+1
Display<=Disp_Decode
end if
end process
process(Disp_Temp) --显示转换
begin
case Disp_Temp is
when 0=>Disp_Decode<="0111111" --0
when 1=>Disp_Decode<="0000110" --1
when 2=>Disp_Decode<="1011011" --2
when 3=>Disp_Decode<="1001111" --3
when 4=>Disp_Decode<="1100110" --4
when 5=>Disp_Decode<="1101101" --5
when 6=>Disp_Decode<="1111101" --6
when 7=>Disp_Decode<="0000111" --7
when 8=>Disp_Decode<="1111111" --8
when 9=>Disp_Decode<="1101111" --9
when 10=>Disp_Decode<="1000000" ---
when others=>Disp_Decode<="0000000" --全灭
end case
end process
end behave
library ieeeuse ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity MINSECONDb is
port(clk,clrm,stop:in std_logic----时钟/清零信号
secm1,secm0:out std_logic_vector(3 downto 0)----秒高位/低位
co:out std_logic)-------输出/进位信号
end MINSECONDb
architecture SEC of MINSECONDb is
signal clk1,DOUT2:std_logic
begin
process(clk,clrm)
variable cnt1,cnt0:std_logic_vector(3 downto 0)---计数
VARIABLE COUNT2 :INTEGER RANGE 0 TO 10
begin
IF CLK'EVENT AND CLK='1'THEN
IF COUNT2>=0 AND COUNT2<10 THEN
COUNT2:=COUNT2+1
ELSE COUNT2:=0
DOUT2<= NOT DOUT2
END IF
END IF
if clrm='1' then----当clr为1时，高低位均为0
cnt1:="0000"
cnt0:="0000"
elsif clk'event and clk='1' then
if stop='1' then
cnt0:=cnt0
cnt1:=cnt1
end if
if cnt1="1001" and cnt0="1000" then----当记数为98（实际是经过59个记时脉冲）
co<='1'----进位
cnt0:="1001"----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1----计数
--elsif cnt0="1001" then
--clk1<=not clk1
else
cnt0:="0000"
if cnt1<"1001" then----高位小于9时
cnt1:=cnt1+1
else
cnt1:="0000"
co<='0'
end if
end if
end if
secm1<=cnt1
secm0<=cnt0
end process
end SEC
秒模块程序清单
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity SECOND is
port(clk,clr:in std_logic----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0)----秒高位/低位
co:out std_logic)-------输出/进位信号
end SECOND
architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0)---计数
begin
if clr='1' then----当ckr为1时，高低位均为0
cnt1:="0000"
cnt0:="0000"
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then----当记数为58（实际是经过59个记时脉冲）
co<='1'----进位
cnt0:="1001"----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1----计数
else
cnt0:="0000"
if cnt1<"0101" then----高位小于5时
cnt1:=cnt1+1
else
cnt1:="0000"
co<='0'
end if
end if
end if
sec1<=cnt1
sec0<=cnt0
end process
end SEC
分模块程序清单
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity MINUTE is
port(clk,en:in std_logic
min1,min0:out std_logic_vector(3 downto 0)
co:out std_logic)
end MINUTE
architecture MIN of MINUTE is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0)
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1'
cnt0:="1001"
elsif cnt0<"1001" then
cnt0:=cnt0+1
else
cnt0:="0000"
if cnt1<"0101" then
cnt1:=cnt1+1
else
cnt1:="0000"
co<='0'
end if
end if
end if
end if
min1<=cnt1
min0<=cnt0
end process
end MIN
时模块程序清单
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity HOUR is
port(clk,en:in std_logic----输入时钟/高电平有效的使能信号
h1,h0:out std_logic_vector(3 downto 0))----时高位/低位
end HOUR
architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0)----记数
begin
if clk'event and clk='1' then---上升沿触发
if en='1' then---同时“使能”为1
if cnt1="0010" and cnt0="0011" then
cnt1:="0000"----高位/低位同时为0时
cnt0:="0000"
elsif cnt0<"1001" then----低位小于9时，低位记数累加
cnt0:=cnt0+1
else
cnt0:="0000"
cnt1:=cnt1+1-----高位记数累加
end if
end if
end if
h1<=cnt1
h0<=cnt0
end process
end hour_arc
动态扫描模块
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
use ieee.std_logic_arith.all
entity SELTIME is
port(
clk:in std_logic------扫描时钟
secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0)-----分别为秒个位/时位；分个位/
daout:out std_logic_vector(3 downto 0)----------------输出
sel:out std_logic_vector(2 downto 0))-----位选信号
end SELTIME
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0)----计数信号
begin
sel<=count
process(clk)
begin
if(clk'event and clk='1') then
if(count>="111") then
count<="000"
else
count<=count+1
end if
end if
case count is
when"111"=>daout<= secm0----秒个位
when"110"=>daout<= secm1----秒十位
when"101"=>daout<= sec0----分个位
when"100"=>daout<= sec1----分十位
when"011"=>daout<=min0 ----时个位
when"010"=>daout<=min1----时十位
when"001"=>daout<=h0
when others =>daout<=h1
end case
end process
end fun
报时模块
library ieee
use ieee.std_logic_1164.all
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0)------输入秒、分高/低位信号
clk:in std_logic------高频声控制
q500,qlk:out std_logic)----低频声控制
end ALERT
architecture sss_arc of ALERT is
begin
process(clk)
begin
if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then----当秒高位为5，低位为9时且分高位为5
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then---当分的低位为1或3或5或7时
q500<='1'----低频输出为1
else
q500<='0'----否则输出为0
end if
end if
if m1="0101" and m0="1001" and s1="0101" and s0="1001" then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”
qlk<='1'-----高频输出为1
else
qlk<='0'
end if
end if
end process
end sss_arc
显示模块
library ieee
use ieee.std_logic_1164.all
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0)----连接seltime扫描部分d信号
q:out std_logic_vector(6 downto 0))----输出段选信号（电平）
end DISPLAY
architecture disp_are of DISPLAY is
begin
process(d)
begin
case d is
when"0000" =>q<="0111111"--显示0
when"0001" =>q<="0000110"--显示1
when"0010" =>q<="1011011"--显示2
when"0011" =>q<="1001111"--显示3
when"0100" =>q<="1100110"--显示4
when"0101" =>q<="1101101"--显示5
when"0110" =>q<="1111101"--显示6
when"0111" =>q<="0100111"--显示7
when"1000" =>q<="1111111"--显示8
when others =>q<="1101111"--显示9
end case
end process
end disp_are
顶层文件（原理图输入）
********************************************************************
数字钟设计模块与程序（不含秒表）
*********************************************************************
1.分频模块（原理图输入）
2. 秒模块程序
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity SECOND is
port(clk,clr:in std_logic
sec1,sec0:out std_logic_vector(3 downto 0)
co:out std_logic)
end SECOND
architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0)
begin
if clr='1' then
cnt1:="0000"
cnt0:="0000"
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then
co<='1'
cnt0:="1001"
elsif cnt0<"1001" then
cnt0:=cnt0+1
else
cnt0:="0000"
if cnt1<"0101" then
cnt1:=cnt1+1
else
cnt1:="0000"
co<='0'
end if
end if
end if
sec1<=cnt1
sec0<=cnt0
end process
end SEC
3.分模块程序
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity MINUTE is
port(clk,en:in std_logic
min1,min0:out std_logic_vector(3 downto 0)
co:out std_logic)
end MINUTE
architecture MIN of MINUTE is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0)
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1'
cnt0:="1001"
elsif cnt0<"1001" then
cnt0:=cnt0+1
else
cnt0:="0000"
if cnt1<"0101" then
cnt1:=cnt1+1
else
cnt1:="0000"
co<='0'
end if
end if
end if
end if
min1<=cnt1
min0<=cnt0
end process
end MIN
4.时模块程序
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity HOUR is
port(clk,en:in std_logic
h1,h0:out std_logic_vector(3 downto 0))
end HOUR
architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0)
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0010" and cnt0="0011" then
cnt1:="0000"
cnt0:="0000"
elsif cnt0<"1001" then
cnt0:=cnt0+1
end if
end if
end if
h1<=cnt1
h0<=cnt0
end process
end hour_arc
5.扫描模块程序
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
use ieee.std_logic_arith.all
entity SELTIME is
port(
clk:in std_logic
sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0)
daout:out std_logic_vector(3 downto 0)
sel:out std_logic_vector(2 downto 0))
end SELTIME
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0)
begin
sel<=count
process(clk)
begin
if(clk'event and clk='1') then
if(count>="101") then
count<="000"
else
count<=count+1
end if
end if
case count is
when"000"=>daout<= sec0
when"001"=>daout<= sec1
when"010"=>daout<= min0
when"011"=>daout<= min1
when"100"=>daout<=h0
when others =>daout<=h1
end case
end process
end fun
6.显示模块程序
library ieee
use ieee.std_logic_1164.all
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0)
q:out std_logic_vector(6 downto 0))
end DISPLAY
architecture disp_are of DISPLAY is
begin
process(d)
begin
case d is
when"0000" =>q<="0111111"
when"0001" =>q<="0000110"
when"0010" =>q<="1011011"
when"0011" =>q<="1001111"
when"0100" =>q<="1100110"
when"0101" =>q<="1101101"
when"0110" =>q<="1111101"
when"0111" =>q<="0100111"
when"1000" =>q<="1111111"
when others =>q<="1101111"
end case
end process
end disp_are
7.定时闹钟模块程序
library ieee
use ieee.std_logic_1164.all
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0)
clk:in std_logic
q500,qlk:out std_logic)
end ALERT
architecture sss_arc of ALERT is
begin
process(clk)
begin
if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then
q500<='1'
else
q500<='0'
end if
end if
if m1="0101" and m0="1001" and s1="0101" and s0="1001" then
qlk<='1'
else
qlk<='0'
end if
end if
end process
end sss_arc
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