LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY DVF IS
PORT(CLK:IN STD_LOGIC ----时钟输入---
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0) ----这个输入11111111-1010=1110101即是十分频----
FOUT:OUT STD_LOGIC)----对CLK十分频后的输出----
END
ARCHITECTURE ONE OF DVF IS
SIGNAL FULL:STD_LOGIC
SIGNAL F_T:STD_LOGIC
BEGIN
P_REG:PROCESS(CLK)
VARIABLE CNT8:STD_LOGIC_VECTOR(7 DOWNTO 0)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNT8="11111111"THEN
CNT8:=D
FULL<='1'
ELSE CNT8:=CNT8+1
FULL<='0'
END IF
END IF
END PROCESS P_REG
P_DIV:PROCESS(FULL)
VARIABLE CNT2:STD_LOGIC
BEGIN
IF FULL'EVENT AND FULL='1' THEN
CNT2:=NOT CNT2
IF CNT2='1' THEN
F_T<='1'
ELSE F_T<='0'
END IF
END IF
END PROCESS P_DIV
FOUT<=F_T
END
倍频是不可能的，FPGA的PLL输入频率是有限制的，另外也没这么多PLL让你用。建议你用查找表的方法实现，具体可以参考FPGA的DDS设计（就是生正弦波），百度文库里一堆一堆的，你把正弦波查找表换成方波的查找表就行了。library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
entity showSeg is
port ( clk : in std_logic--1k时钟
seg : buffer std_logic--片选信号，高电平选择高位，低电平选择低位
dout : out std_logic_vector (6 downto 0)--输出信号
)
end showSeg
architecture behav of showSeg is
signal clk_1Hz : std_logic--分频
signal cnt_div : std_logic_vector (9 downto 0)--分频计数值
signal show_num : std_logic_vector (7 downto 0)--待显示的数值，0~255你要求的数值
signal temp : std_logic_vector (3 downto 0)--中间信号
begin
process(clk)--预分频进程
variable flag : std_logic
begin
if clk'event and clk='1' then
if cnt_div<="0111110011" then --499占空比50%
cnt_div<=cnt_div+"0000000001"
else
cnt_div<="0000000000"
if flag='1' then clk_1Hz<='1'flag:='0'
elsif flag='0' then clk_1Hz<='0'flag:='1'
end if
end if
end if
end process
process(clk_1Hz)--计数进程，计算9 19 29 。。。91 92 。。。190.。。。一共43组数值
variable cyc : std_logic_vector (7 downto 0)
begin
if clk_1Hz'event and clk_1Hz='1' then
if cyc<="00101010" then --42
cyc:=cyc+"00000001"
else cyc:="00000000"
show_num<="00001001"--9
end if
if cyc>="00001001" and cyc<="00010010" then
show_num<=show_num+"00000001"--90,91,...,99
elsif cyc>="00011100" and cyc<="00100101" then
show_num<=show_num+"00000001"--190,191,...,199
else show_num<=show_num+"00001010"--others
end if
end if
end process
process(clk,show_num)--输出显示进程，500hz频率扫描
begin
if clk'event and clk='1' then
if seg='1' then
temp<=show_num(3 downto 0)--显示低位数值
seg<='0'
elsif seg='0' then
temp<=show_num(7 downto 4)--显示高位数值
seg<='1'
end if
case temp is --共阴极数码管
when "0000" =>dout<="0111111"--0
when "0001" =>dout<="0000110"--1
when "0010" =>dout<="1011011"--2
when "0011" =>dout<="1001111"--3
when "0100" =>dout<="1100110"--4
when "0101" =>dout<="1101101"--5
when "0110" =>dout<="1111101"--6
when "0111" =>dout<="0000111"--7
when "1000" =>dout<="1111111"--8
when "1001" =>dout<="1100111"--9
when "1010" =>dout<="1110111"--A
when "1011" =>dout<="1111000"--B这里显示小写b
when "1100" =>dout<="0111001"--C
when "1101" =>dout<="1011110"--D这里显示小写d
when "1110" =>dout<="1111001"--E
when "1111" =>dout<="1110001"--F
end case
end if
end process
end behav
编了几个小时，水平不怎么样，编译没问题，仿真结果就不知道了，仅供参考，希望给我分~欢迎分享，转载请注明来源：内存溢出
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