FPGA外部能输入高低电平怎么检测 然后输出两个引脚的VHDL程序

直接判断输出就可以了。

LIBRARY ieee

USE ieee.std_logic_1164.all

USE ieee.std_logic_arith.all

USE ieee.std_logic_unsigned.ALL

ENTITY bit_detect IS

PORT

(

data1b_in : in std_logic

data2b_out: out std_logic_vector(1 downto 0)

)

END bit_detect

ARCHITECTURE arc OF bit_detect is

BEGIN

data2b_out<="10" when data1b_in='1' else

"01" when data1b_in='0' else

"ZZ"

END arc

没有clk引入，没有D触发器，怎么实现上升沿检测啊？

PROCESS(clkTemp)

BEGIN

if rising_edge(clkTemp) then

dsp_wrmTmp1<=dsp_wrmTmp

dsp_wrmTmp2<=dsp_wrmTmp1

endif

END PROCESS

PROCESS(clkTemp,rdint,dsp_wrmTmp,wr_fifo)

BEGIN

if rising_edge(clkTemp) then

if(dsp_wrmTmp='1' and dsp_wrmTmp2='0')then

TP<='1'

elsif(dsp_wrmTmp='0' and dsp_wrmTmp2='1')then

TP<='0'

end if

endif

END PROCESS

个人认为你的clkTemp就是你时钟。

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