&soc {
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm"; //设备节点的compatible属性，用来匹配驱动
reg = <0x1c00000 0x3000>,
<0x1c06000 0x2000>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>,
<0x1c03000 0x1000>; //寄存器区域：<寄存器基地址 所占空间>
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"mhi"; //寄存器区域名称
cell-index = <0>; //片选号
linux,pci-domain = <0>; //Linux pci域序号
#address-cells = <3>; //基地址、片选号等绝对起始地址所占字长（u32）
#size-cells = <2>; //地址长度所占字长（u32）
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; //地址转换表，local->parent
interrupt-parent = <&pcie0>; //此设备节点所属的中断控制器，如果未设置该属性，会自动依附父节点的
interrupts = <0 1 2 3 4>; //中断控制器编号
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d"; //中断控制器名称，int_global_int为全局中断控制器
#interrupt-cells = <1>; //中断控制器节点的属性，用来标识这个控制器需要几个单位做中断描述符
interrupt-map-mask = <0 0 0 0xffffffff>; //由中断产生设备的地址和中断源组成，因为#address-cells = <3>，所以中断源用1个u32表示，中断产生设备地址由3个u32组成
interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; //<中断设备地址的第一个u32 中断设备地址的第二个u32 中断设备地址的第三个u32 中断设备的中断源 中断类型 中断号 中断触发条件>
msi-parent = <&pcie0_msi>; //指定msi中断控制器
perst-gpio = <&tlmm 57 0>; //指定reset功能的gpio，
wake-gpio = <&tlmm 53 0>; //指定wake功能的gpio，
pinctrl-names = "default", "sleep"; //pinctrl名称，对应pinctrl.dtsi中的配置
pinctrl-0 = <&pcie0_clkreq_default
&pcie0_perst_default
&pcie0_wake_default>; //pinctrl-0的三个gpio配置，pinctrl.dtsi中进行对应配置
pinctrl-1 = <&pcie0_clkreq_sleep
&pcie0_perst_default
&pcie0_wake_default>; //pinctrl-1的三个gpio配置，pinctrl.dtsi中进行对应配置
gdsc-vdd-supply = <&gcc_pcie_gdsc>; //gdsc-vdd对应电源域名称
vreg-1p8-supply = <&pmx65_l1>; //vreg-1p8对应电源域名称
vreg-0p9-supply = <&pmx65_l4>; //vreg-0p9对应电源域名称
vreg-cx-supply = <&VDD_CX_LEVEL>; //vreg-cx对应电源域名称
vreg-mx-supply = <&VDD_MXA_LEVEL>; //vreg-mx对应电源域名称
qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; //vreg-1p8电压范围，<最高电压 默认电压 最低电压>
qcom,vreg-0p9-voltage-level = <912000 912000 132000>;
qcom,vreg-cx-voltage-level = ;
qcom,vreg-mx-voltage-level = ;
qcom,bw-scale =
; //PCIe带宽扩展
interconnect-names = "icc_path";
interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_AUX_CLK>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
<&gcc GCC_PCIE_PIPE_CLK_SRC>,
<&pcie_pipe_clk>; //时钟控制器
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_0_sleep_clk", "pcie_phy_refgen_clk",
"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; //时钟名称
max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>; //时钟频率
resets = <&gcc GCC_PCIE_BCR>,
<&gcc GCC_PCIE_PHY_BCR>; //reset控制器
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset"; //区分reset配置名称
qcom,smmu-sid-base = <0x0200>; //SMMU把CPU提交给设备的VA地址，直接作为设备发出的地址，变成正确的物理地址，访问到物理内存上，用stream id作区分
iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
<0x100 &apps_smmu 0x0201 0x1>; //
qcom,aux-clk-freq = <17>;
qcom,tpwr-on-scale = <1>;
qcom,tpwr-on-value = <9>;
qcom,eq-fmdc-t-min-phase23 = <1>;
qcom,slv-addr-space-size = <0x40000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,pcie-phy-ver = <1108>;
qcom,phy-status-offset = <0x1214>;
qcom,phy-status-bit = <7>;
qcom,phy-power-down-offset = <0x1240>;
qcom,phy-sequence = <0x1240 0x03 0x0
0x1010 0x01 0x0
0x101c 0x31 0x0
0x1020 0x01 0x0
0x1024 0xde 0x0
0x1028 0x07 0x0
0x1030 0x97 0x0
0x1034 0x0c 0x0
0x1044 0x14 0x0
0x1048 0x90 0x0
0x1058 0x0f 0x0
0x1074 0x06 0x0
0x1078 0x06 0x0
0x107c 0x16 0x0
0x1080 0x16 0x0
0x1084 0x36 0x0
0x1088 0x36 0x0
0x1094 0x08 0x0
0x10a4 0x46 0x0
0x10a8 0x04 0x0
0x10ac 0x0a 0x0
0x10b0 0x1a 0x0
0x10b4 0x14 0x0
0x10b8 0x34 0x0
0x10bc 0x82 0x0
0x10c4 0xd0 0x0
0x10cc 0x55 0x0
0x10d0 0x55 0x0
0x10d4 0x03 0x0
0x10d8 0x55 0x0
0x10dc 0x55 0x0
0x10e0 0x05 0x0
0x110c 0x02 0x0
0x1154 0x34 0x0
0x1158 0x12 0x0
0x115c 0x00 0x0
0x1168 0x0a 0x0
0x116c 0x04 0x0
0x119c 0x88 0x0
0x1174 0x60 0x0
0x117c 0x06 0x0
0x11a0 0x14 0x0
0x11a8 0x0f 0x0
0x0220 0x16 0x0
0x03c0 0x38 0x0
0x0a20 0x16 0x0
0x0bc0 0x38 0x0
0x0364 0xcc 0x0
0x0368 0x12 0x0
0x036c 0xcc 0x0
0x0374 0x4a 0x0
0x0378 0x29 0x0
0x037c 0xc5 0x0
0x0380 0xac 0x0
0x0384 0xb6 0x0
0x0388 0xc0 0x0
0x038c 0x07 0x0
0x0390 0xfb 0x0
0x0394 0x0d 0x0
0x0398 0xc5 0x0
0x039c 0xee 0x0
0x03a0 0xbf 0x0
0x03a4 0xa0 0x0
0x03a8 0x81 0x0
0x03ac 0xde 0x0
0x03b0 0x7f 0x0
0x0b64 0xcc 0x0
0x0b68 0x12 0x0
0x0b6c 0xcc 0x0
0x0b74 0x4a 0x0
0x0b78 0x29 0x0
0x0b7c 0xc5 0x0
0x0b80 0xac 0x0
0x0b84 0xb6 0x0
0x0b88 0xc0 0x0
0x0b8c 0x07 0x0
0x0b90 0xfb 0x0
0x0b94 0x0d 0x0
0x0b98 0xc5 0x0
0x0b9c 0xee 0x0
0x0ba0 0xbf 0x0
0x0ba4 0xa0 0x0
0x0ba8 0x81 0x0
0x0bac 0xde 0x0
0x0bb0 0x7f 0x0
0x03b4 0x20 0x0
0x022c 0x3f 0x0
0x0230 0x37 0x0
0x0bb4 0x20 0x0
0x0a2c 0x3f 0x0
0x0a30 0x37 0x0
0x0078 0x05 0x0
0x007c 0xf6 0x0
0x0878 0x05 0x0
0x087c 0xf6 0x0
0x0290 0x05 0x0
0x0a90 0x05 0x0
0x03f8 0x1f 0x0
0x0400 0x1f 0x0
0x0408 0x1f 0x0
0x0410 0x1f 0x0
0x0418 0x1f 0x0
0x0420 0x1f 0x0
0x03f4 0x1f 0x0
0x03fc 0x1f 0x0
0x0404 0x1f 0x0
0x0bf8 0x1f 0x0
0x0c00 0x1f 0x0
0x0c08 0x1f 0x0
0x0c10 0x1f 0x0
0x0c18 0x1f 0x0
0x0c20 0x1f 0x0
0x0bf4 0x1f 0x0
0x0bfc 0x1f 0x0
0x0c04 0x1f 0x0
0x0208 0x0c 0x0
0x0a08 0x0c 0x0
0x020c 0x0a 0x0
0x0a0c 0x0a 0x0
0x02dc 0x0a 0x0
0x0adc 0x0a 0x0
0x0308 0x0b 0x0
0x0b08 0x0b 0x0
0x027c 0x10 0x0
0x0a7c 0x10 0x0
0x02b4 0x00 0x0
0x0ab4 0x00 0x0
0x02ec 0x0f 0x0
0x0aec 0x0f 0x0
0x02c4 0x00 0x0
0x02c8 0x1f 0x0
0x0ac4 0x00 0x0
0x0ac8 0x1f 0x0
0x0030 0x1a 0x0
0x0034 0x0c 0x0
0x0830 0x1a 0x0
0x0834 0x0c 0x0
0x141c 0xc1 0x0
0x1490 0x00 0x0
0x13e0 0x16 0x0
0x13e4 0x22 0x0
0x1508 0x02 0x0
0x14a0 0x16 0x0
0x1584 0x28 0x0
0x1370 0x2e 0x0
0x155c 0x2e 0x0
0x140c 0x1d 0x0
0x1388 0xaa 0x0
0x1200 0x00 0x0
0x1244 0x03 0x0>; //驱动初始化序列
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
};
pcie0_msi: qcom,pcie0_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = ,
,
,
,
,
,
,
;
qcom,snps;
};
};
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