怎样用VHDL设计含有异步清零和同步时钟使能的10位加法计数器

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_unsignedall;

entity add is

port(clr,en,clkin:in std_logic; ---------清零,使能及触发时钟

a,b:in std_logic_vector(9 downto 0);---------加数

c:out std_logic_vector(9 downto 0);----------和

ci:out std_logic ---------进位

);

end add;

architecture arch of add is

---------;

signal reg:std_logic_vector(10 downto 0):="00000000000";

----------------------------------------------------------------------------

begin

----------------

process(clr,clkin,en,a,b)

begin

if(clr='0') then --------------异步清零

reg

我用quartusⅡ已编译并且仿真都对的，我写的是0亮1灭，如果实际情况与这相反，你自己倒一下。

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_SIGNEDALL;

USE IEEEnumeric_stdall;

ENTITY test IS

PORT (clock: in std_logic; -----clock1加48MHz的信号

row: out std_logic_vector(0 to 7));

END test;

ARCHITECTURE behave OF test IS

CONSTANT fp_clka:INTEGER:=12000000; ---扫描信号频率为2Hz

SIGNAL a: INTEGER RANGE 0 TO 12000001;

signal saomiao :integer range 0 to 9;

SIGNAL clka: std_logic;

BEGIN

PROCESS (clock)

BEGIN

IF rising_edge(clock) THEN

IF a<fp_clka then --clka

a<=a+1;

clka<=clka;

ELSE

a<=0;

clka<= NOT clka;

end if;

end if;

end process;

process(clka)

BEGIN

IF rising_edge(clka) THEN

saomiao<=saomiao+1;

if saomiao=9 then

saomiao<=0;

end if;

case saomiao is ---'1'代表不亮,'0'代表亮

when 0 =>row<="01111111";

when 1 =>row<="10111111";

when 2 =>row<="11011111";

when 3 =>row<="11101111";

when 4 =>row<="11110111";

when 5 =>row<="11111011";

when 6 =>row<="11111101";

when 7 =>row<="11111110";

when 8 =>row<="00000000";

when others =>row<="11111111";

END CASE;

END IF;

end process;

END behave;

以下有一个波形仿真过了，但是下载时有点问题的代码，如果你解决了告诉我哈，谢谢

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_unsignedALL;

USE IEEESTD_LOGIC_ARITHALL;

ENTITY PAOBIAO IS

PORT(

CLK,CLR,PAUSE:IN STD_LOGIC;

cs1:OUT std_logic_vector(6 DOWNTO 0);

cs2:OUT std_logic_vector(6 DOWNTO 0);

s1:OUT std_logic_vector(6 DOWNTO 0);

s2:OUT std_logic_vector(6 DOWNTO 0);

m1:OUT std_logic_vector(6 DOWNTO 0);

m2:OUT std_logic_vector(6 DOWNTO 0));

END PAOBIAO;

ARCHITECTURE PAOBIAO_ARCH OF PAOBIAO IS

signal ics1,ics2,is1,im1:UNSIGNED (3 DOWNTO 0);

signal is2,im2:UNSIGNED (2 DOWNTO 0);

BEGIN

PROCESS(CLK,ics1,ics2,is1,im1,is2,im2)

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

IF CLR='1' THEN ics1<=(others=>'0');ics2<=(others=>'0');is1<=(others=>'0');im1<=(others=>'0');is2<=(others=>'0');im2<=(others=>'0');

ELSIF PAUSE='0' THEN

IF (ics1=9) then ics1<=(others=>'0');

IF (ics2=9) then ics2<=(others=>'0');

IF (is1=9) then is1<=(others=>'0');

IF (is2=5) then is2<=(others=>'0');

IF (im1=9) then im1<=(others=>'0');

IF (im2=5) then ics1<=(others=>'0');ics2<=(others=>'0');is1<=(others=>'0');im1<=(others=>'0');is2<=(others=>'0');im2<=(others=>'0');

ELSE im2<=im2+1;END IF;

ELSE im1<=im1+1;END IF;

ELSE is2<=is2+1;END IF;

ELSE is1<=is1+1;END IF;

ELSE ics2<=ics2+1;END IF;

ELSE ics1<=ics1+1; END IF;

ELSE ics1<=ics1;ics2<=ics2;is1<=is1;im1<=im1;is2<=is2;im2<=im2;

END IF;

END IF;

CASE ics1 is

WHEN "0000" => cs1<="1111110";

WHEN "0001" => cs1<="0110000";

WHEN "0010" => cs1<="1101101";

WHEN "0011" => cs1<="1111001";

WHEN "0100" => cs1<="0110011";

WHEN "0101" => cs1<="1011011";

WHEN "0110" => cs1<="1011111";

WHEN "0111" => cs1<="1110000";

WHEN "1000" => cs1<="1111111";

WHEN "1001" => cs1<="1111011";

WHEN OTHERS =>null;

END CASE;

CASE ics2 is

WHEN "0000" => cs2<="1111110";

WHEN "0001" => cs2<="0110000";

WHEN "0010" => cs2<="1101101";

WHEN "0011" => cs2<="1111001";

WHEN "0100" => cs2<="0110011";

WHEN "0101" => cs2<="1011011";

WHEN "0110" => cs2<="1011111";

WHEN "0111" => cs2<="1110000";

WHEN "1000" => cs2<="1111111";

WHEN "1001" => cs2<="1111011";

WHEN OTHERS =>null;

END CASE;

CASE is1 is

WHEN "0000" => s1<="1111110";

WHEN "0001" => s1<="0110000";

WHEN "0010" => s1<="1101101";

WHEN "0011" => s1<="1111001";

WHEN "0100" => s1<="0110011";

WHEN "0101" => s1<="1011011";

WHEN "0110" => s1<="1011111";

WHEN "0111" => s1<="1110000";

WHEN "1000" => s1<="1111111";

WHEN "1001" => s1<="1111011";

WHEN OTHERS =>null;

END CASE;

CASE is2 is

WHEN "000" => s2<="1111110";

WHEN "001" => s2<="0110000";

WHEN "010" => s2<="1101101";

WHEN "011" => s2<="1111001";

WHEN "100" => s2<="0110011";

WHEN "101" => s2<="1011011";

WHEN OTHERS =>null;

END CASE;

CASE im1 is

WHEN "0000" => m1<="1111110";

WHEN "0001" => m1<="0110000";

WHEN "0010" => m1<="1101101";

WHEN "0011" => m1<="1111001";

WHEN "0100" => m1<="0110011";

WHEN "0101" => m1<="1011011";

WHEN "0110" => m1<="1011111";

WHEN "0111" => m1<="1110000";

WHEN "1000" => m1<="1111111";

WHEN "1001" => m1<="1111011";

WHEN OTHERS =>null;

END CASE;

CASE im2 is

WHEN "000" => m2<="1111110";

WHEN "001" => m2<="0110000";

WHEN "010" => m2<="1101101";

WHEN "011" => m2<="1111001";

WHEN "100" => m2<="0110011";

WHEN "101" => m2<="1011011";

WHEN OTHERS =>null;

END CASE;

END PROCESS;

END PAOBIAO_ARCH;

以上就是关于怎样用VHDL设计含有异步清零和同步时钟使能的10位加法计数器全部的内容，包括:怎样用VHDL设计含有异步清零和同步时钟使能的10位加法计数器、用VHDL语言编写程序、求一个数字跑表VHDL程序，（时钟输入（CLK）、复位（CLR）和启动/暂停（PAUSE））等相关内容解答，如果想了解更多相关内容，可以关注我们，你们的支持是我们更新的动力！