数字逻辑 秒表设计

#include<reg51h>

#define uchar unsigned char

unsigned char code timeshow[]={ 0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90,0x88,0x83,0xC6,0xA1,0x86,0x8E};

unsigned char code timeshow1[]={0x40,0x79,0x24,0x30,0x19,0x12,0x02,0x78,0x00,0x10,0x08,0x03,0x46,0x21,0x06,0x0E};

sbit minshi=P2^0;

sbit minge=P2^1;

sbit secshi=P2^2;

sbit secge=P2^3;

uchar min=0,second=0;

uchar timercounter=0;

uchar AN=0;

/延时200us程序/

void delay200us()

{

uchar i;

for(i=100;i>0;i++);

}

void delay()

{

uchar i,j;

for(i=200;i>0;i--)

for(j=250;j>0;j--);

}

void desply(uchar min, uchar second)

{

minshi=0;

P0=timeshow[min/10];

delay200us();

minshi=1;

minge=0;

P0=timeshow1[min%10];

delay200us();

minge=1;

secshi=0;

P0=timeshow[second/10];

delay200us();

secshi=1;

secge=0;

P0=timeshow[second%10];

delay200us();

secge=1;

}

/定时器初始化程序/

void Init_timer()

{

EA=0;

TR0=0;

TMOD=0x01; //计数器0，方式1

EA=1;

ET0=1;

while(1)

{

if(INT0==0)

{

delay();

if(INT0==0)

AN++;

if(AN>3)

AN=0;

switch(AN)

{

case(1):TR0=1; TH0=(65536-10000)/256; //定时10ms

TL0=(65536-10000)%256;

break;

case(2):TR0=0; break;

case(3):AN=0;min=0;second=0; break;

}

delay();

}

desply(min,second);

}

}

/中断处理程序/

void t0() interrupt 1 using 0

{

second++;

if(second==100)

{

second=0;

min++;

}

if(min==60)

min=0;

else

{

TH0=(65536-10000)/256;

TL0=(65536-10000)%256;

}

}

/主程序/

void main()

{

P2=0xff;

P0=0xff;

Init_timer();

}

这个是用定时器做的，比较精确，我是用我编的时钟程序改的，里面的min,second分别对应秒表的秒和百分秒。 你如果要分的话就在中断程序里改下，再简单改下显示程序的个数就好了

数字秒表电路的设计

一、设计要求

设计用于体育比赛的数字秒表，要求：

⑴计时器能显示 001s的时间。

m ⑵计时器的最长计时时间为 24h。

总体框图如图2所示

二、模块及模块的功能

⑴ 100进制计数器模块BAI见图2 1, 输出值为 001s和01s。

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_unsignedall;

entity bai is

port( clr ,clk: in std_logic;

bai1,bai0:out std_logic_vector(3 downto 0);

c0: out std_logic);

end bai;

architecture bai_arc of bai is

begin

process(clk, clr)

variable cnt0,cnt1:std_logic_vector(3 downto 0);

begin

if clr ='0'then

cnt0:="0000";

cnt1:="0000";

elsif clk'event and clk='1' then

if cnt0 ="1000"and cnt1 ="1001"then

cnt0:="1001";

c0<='1';

elsif cnt0 <"1001" then

cnt0:=cnt0+1;

else cnt0:="0000";

if cnt1 <"1001" then

cnt1:=cnt1+1;

else

cnt1:="0000";

c0<='0';

end if;

end if;

end if;

bai1<=cnt1;

bai0<=cnt0;

end process;

end bai_arc;

⑵ 60进制计数器模块MIAO见图22,用于对秒和分的计数。

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_unsignedall;

entity miao is

port(clr,clk,en:in std_logic;

sec1,sec0:out std_logic_vector(3 downto 0);

c0:out std_logic);

end miao;

architecture miao_arc of miao is

begin

process(clk,clr)

variable cnt0,cnt1:std_logic_vector(3 downto 0);

begin

if clr='0'then

cnt0:="0000";

cnt1:="0000";

elsif clk'event and clk='1'then

if en='1'then

if cnt1="0101" and cnt0="1000"then

cnt0:="1001"; c0<='1';

elsif cnt0<"1001"then

cnt0:=cnt0+1;

else cnt0:="0000";

if cnt1<"0101"then

cnt1:=cnt1+1;

else

cnt1:="0000";

c0<='0';

end if;

end if;

end if;

end if;

sec1<=cnt1;

sec0<=cnt0;

end process;

end miao_arc;

⑶ 24进制计数器模块HOU见图2 3, 计数输出为小时的数值。

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_unsignedall;

entity hou is

port(en,clk,clr:in std_logic;

h1,h0:out std_logic_vector(3 downto 0));

end hou;

architecture hour_arc of hou is

begin

process(clk)

variable cnt0,cnt1:std_logic_vector(3 downto 0);

begin

if clr='0'then

cnt0:="0000";

cnt1:="0000";

elsif clk'event and clk='1'then

if en='1'then

if cnt0="0011" and cnt1="0010"then

cnt0:="0000"; cnt1:="0000";

elsif cnt0<"1001"then

cnt0:=cnt0+1;

else

cnt0:="0000";

cnt1:=cnt1+1;

end if;

end if;

end if;

h1<=cnt1;

h0<=cnt0;

end process;

end hour_arc;

⑷同步消除抖动模块 DOU见图24。

library ieee;

use ieeestd_logic_1164all;

entity dou is

port(din,clk:in std_logic;

dout:out std_logic);

end dou;

architecture dou_arc of dou is

signal x,y:std_logic;

begin

process(clk)

begin

if clk'event and clk='1'then

x<=din;

y<=x;

end if;

dout<=x and(not y);

end process;

end dou_arc;

⑸启停控制模块 AAB见图25。秒表的启停是通过控制送给计数器的时钟来实现的，当按下启停键后，输出端Q的状态发生反转。Q为‘1'时，时钟可通过与门，秒表计时；Q为‘0'时，时钟被屏蔽，计数器得不到时钟，停止计数。

library ieee;

use ieeestd_logic_1164all;

entity aab is

port(a,clk,clr:in std_logic;

q:out std_logic);

end aab;

architecture aab_arc of aab is

begin

process(clk)

variable tmp:std_logic;

begin

if clr='0'then tmp:='0';

elsif clk'event and clk='1'then

if a='1'then

tmp:=not tmp;

end if;

end if;

q<=tmp;

end process;

end aab_arc;

⑹产生数码管的片选信号模块 SEL见图26 。

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_unsignedall;

entity sel is

port(clk:in std_logic;

q:out std_logic_vector(2 downto 0));

end sel;

architecture sel_arc of sel is

begin

process(clk)

variable cnt:std_logic_vector(2 downto 0);

begin

if clk'event and clk='1'then

cnt:=cnt+1;

end if;

q<=cnt;

end process;

end sel_arc;

⑺模块 BBC见图27，此模块对应不同的片选信号，输出不同的要显示的数据。

library ieee;

use ieeestd_logic_1164all;

entity bbc is

port(bai1,bai0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);

sel:in std_logic_vector(2 downto 0);

q: out std_logic_vector(3 downto 0));

end bbc;

architecture bbb_arc of bbc is

begin

process(sel)

begin

case sel is

when "000"=>q<=bai0;

when "001"=>q<=bai1;

when "010"=>q<=sec0;

when "011"=>q<=sec1;

when "100"=>q<=min0;

when "101"=>q<=min1;

when "110"=>q<=h0;

when "111"=>q<=h1;

when others=>q<="111";

end case;

end process;

end bbb_arc;

⑻ 模块 CH见图28，该模块为4线—七段译码器。

library ieee;

use ieeestd_logic_1164all;

entity disp is

port(d:in std_logic_vector(3 downto 0);

q:out std_logic_vector(6 downto 0));

end disp;

architecture disp_arc of disp is

begin

process(d)

begin

case d is

when "0000"=>q<="0111111";

when "0001"=>q<="0000110";

when "0010"=>q<="1011011";

when "0011"=>q<="1001111";

when "0100"=>q<="1100110";

when "0101"=>q<="1101101";

when "0110"=>q<="1111101";

when "0111"=>q<="0100111";

when "1000"=>q<="1111111";

when "1001"=>q<="1101111";

when others=>q<="0000000";

end case;

end process;

我一般是查表

就是把 LED管对应的字符代码（和你的硬件连接方式有关系） 0~F列出来

然后 计时就直接用个INT变量累加就完了 然后根据变量值 找出相应的码字进行显示就行了 用个分支语句就可以实现 扫描屏率100有点高波 其实1HZ就足够了 你一秒跳一次刚好

`timescale 1s/01s

module clock(reset);

input reset;

output [5:0] hour,min,sec;

reg[5:0] hour,min,sec;

initial begin

clk=1'b0;

forever #05 clk=~clk;

end

always@(posedge clk or reset)

if(reset)

begin

hour<=6'b0000_0;

min<=6'b0000_0;

sec<=6'b0000_0;

end

elseif(sec!=6'b111011)

begin

sec<=sec+6'b0000_1;

end

elseif(sec==6'b111011)

begin

if( min!=6'b111011)

begin

sec<=6'b0000_0;

min<=min+6'b0000_1;

end

elseif(min==6'b111011)

begin

if(hour!=6'b011000)

begin

hour<=hour+6'b0000_1;

sec<=6'b0000_0;

min<=6'b0000_0;

end

elseif(hour==6'b011000)

begin

hour<=6'b0000_0;

sec<=6'b0000_0;

min<=6'b0000_0;

end

end

always@(hour)

repeat(hour) #1 beats ;

task beats;

//define beats event;

endtask

endmodule

beats事件为响铃 *** 作任务。

参考下这个 只实现了表的功能， 希望对你有帮助

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