verilog mux仿真测试文件怎么写

module mux21(a,b,c,sel);

input a;

input b;

output c;

input sel;

reg c;

always @(a or b or c or sel)

begin

case(sel)

1'b0:c=a;

1'b1:c=b;

endcase

end

endmodule

//test

module mux21_tb;

reg a;

reg b;

reg sel;

initial

begin

a=1'b0;

b=1'b1;

sel=1'b0;

#10

sel=1'b1;

end

$monitor($stime,a,b,sel,,c);

#10_000

$stop;

endmodule

//可以在modelsim中运行一下试试，如果用vcs仿真的话产生波形文件就好了

本人也在用Verilog语言编写程序，之前编写过测试文件，在Quartus中编译总是出错，说不是一个模块之类的，用在Modelsim中就可以实现，因为Modelsim在你启动仿真时，要求你添加源代码和测试文件（不添加测试文件也可以，以用自己给时序，像Quartus一样）。所以本人认为Quartus只能通过建立波形文件来仿真。

你 所谓的并行，是不是说将一串8位二进制码，如上图中x输入转换为并行

然后判断输入x是否等于预置值1010_1101？

还是题目中键4、3 并行输入信号•键 1、2 预置数据

每次并行检测2位，比如判断x输入两位是否等于10，后两位等于10，再两位等于11，最后两位等于01？

如果是这样，可以将x串行输入，进行个串并转换，例如用一个寄存器reg1[1:0]保存其值。

always @ (posedge clk or negedge rst)

if(!rst)

reg1 <= 2'h0;

else

reg1 <= {x, reg1[1]};

然后对比reg1值是否等于预置值。

仅供参考，谢谢

我把原理讲诉一下：

1按键1是 按键2和按键3 的启动控制信号

2按键2 与按键3 是互相矛盾的，只有一个会亮

分析，通过状态机实现，

当light2_ctrl ==1时进入light2状态

当light3_ctrl ==1时进入light3状态

然后请看我下面编写的程序

module delay_1s(

clock,

reset_n,

light1_ena,

light1_on

);

paramter MAX_VALUE = 6'd1000;

input clock;

input reset_n;

input light1_ena;//输入light1的启动信号

output light1_on;//经过1s后，给出light1亮灯信号

reg [5:0] counter;

always@(posedge clock or negedge reset_n)

begin

if(!reset_n)

counter <= 6'b0;

else if(counter<MAX_VALUE&&counter>6'd1)

counter <= counter + 1'b1;

else if(light1_ena)

counter <= 6'b1;

else

counter <=6'd0;

end

reg light1_on;

always@(posedge clock or negedge reset_n)

begin

if(!reset_n)

light1_on <= 1'b0;

else if(counter<=MAX_VALUE)

light1_on<= 1'b1;

end

endmodule

//------------------------------------

module light_ctrl(

clock,

reset_n,

light1_ctrl,

light2_ctrl,

light3_ctrl,

light2_ena,

light3_ena,

time_counter

);

input clock;

input reset_n;//low active

input light1_ctrl;//人按的按键

output light1_ena;//控制灯1亮灭的信号

input light2_ctrl;//人按的按键

output light2_ena;//控制灯1亮灭的信号

input light3_ctrl;//人按的

output light3_ena;//控制灯1亮灭的信号

output [3:0]time_counter; //接 4位的数码管的时间累计值,以clock为基

准的次数

//-----------------------

reg light2_ena;

reg light3_ena;

reg[2:0]curr_state;

reg[2:0]next_state;

reg [3:0]time_counter；

parameter IDLE = 3'b0;

parameter LIGHT1 = 3'b100;

parameter LIGHT2 = 3'b101;

parameter LIGHT3 = 3'b110;

parameter LIGHT_ALL = 3'b111;

//

always@(posedge clock or negedge reset_n)

begin

if(!reset_n)

curr_state <= IDLE;

else

curr_state <= next_state;

end

always@()

begin

next_state = curr_state;

case(curr_state)

IDLE:

if(light1_ctrl)

next_state = LIGHT1;

else

next_state = IDLE;

LIGHT1:

begin

case({light3_ctrl,light2_ctrl})

2'b00: next_state= LIGHT1;

2'b10: next_state= LIGHT3;

2'b01: next_state= LIGHT2;

default: next_state= LIGHT_ALL;//LIGHT_ALL

state

endcase

end//LIGHT1

LIGHT2:

begin

next_state= LIGHT2;

end

LIGHT3:

begin

next_state= LIGHT3;

end

LIGHT_ALL:

begin

next_state= LIGHT_ALL;

end

default: next_state = IDLE;

endcase

end

always@(posedge clock or negedge reset_n)

begin

if(!reset_n)

light2_ena <= 1'b0;

else

light2_ena <= (curr_state==LIGHT2)|(curr_state==LIGHT_ALL);

end

always@(posedge clock or negedge reset_n)

begin

if(!reset_n)

light3_ena <= 1'b0;

else

light3_ena <= (curr_state==LIGHT3)|(curr_state==LIGHT_ALL);

end

always@(posedge clock or negedge reset_n)

begin

if(!reset_n)

time_counter <= 4'b0;

else if(curr_state==LIGHT1)

time_counter <= time_counter + 1'b1;

end

endmodule

//------------------------------------

module light_ctrl_top(

clock,

reset_n,

light1_ctrl,

light2_ctrl,

light3_ctrl,

light1_on,

light2_on,

light3_on,

time_counter

);

input clock;

input reset_n;

input light1_ctrl;

input light2_ctrl;

input light3_ctrl;

output light1_on;

output light2_on;

output light3_on;

output[3:0] time_counter;

//---------------------------

delay_1s u_delay_1s(

clock(clock),

reset_n(reset_n),

light1_ena(light1_ctrl),

light1_on(light1_on)

);

//-----------------------------

light_ctrl u_light_ctrl(

clock(clock),

reset_n(reset_n),

light1_ctrl( light1_on ),

light2_ctrl( light2_ctrl ),

light3_ctrl( light3_ctrl ),

light2_ena(light2_on ),

light3_ena(light2_on ),

time_counter( time_counter)

);

endmodule

module washer(CLK,CLK_baojing,SET,RD,EN,LAMP,COUNT,TIMES,ALARM); //信号定义

output [7:0] COUNT,TIMES;

output [3:0] LAMP;

output ALARM;

input CLK,CLK_baojing,EN,RD;

input [3:0] SET;

reg [7:0] num,tim;

reg temp,C,ALARM;

reg [2:0] count;

reg [7:0] S1,S2,S3,S4;

reg [3:0] LAMP;

wire T,baojing;

assign COUNT=num;

assign TIMES=tim;

assign T=((count==0&&num==2&&LAMP==2)||!EN||RD);

assign baojing=(!tim&&EN);

always // 初始化标志变量

begin

S1<=4'D1000;

S2<=4'D200;

S3<=4'D1000;

S4<=8'h05;

end

always@(posedge CLK)

begin

if(!RD)

begin

C<=0;

if(EN&&!C)

begin if(!temp&&tim) // 洗衣状态

begin

temp<=1;

case (count)

0: begin num<=S1;LAMP<=4;count<=1;end

1: begin num<=S2;LAMP<=2;count<=2;end

2: begin num<=S3;LAMP<=1;count<=3;end

3: begin num<=S4;LAMP<=2;count<=0;end

default LAMP<=2;

endcase

end

else

begin // 排水 *** 作

if(num>1)

if(num[3:0]==0)

begin

num[3:0]<=4'b1001;

num[7:4]<=num[7:4]-1;

end

else num[3:0]<=num[3:0]-1;

if(num==2)temp<=0;

if(num==1)temp<=0;

end

end

end

else

begin

count<=0;

num<=0;

temp<=0;

LAMP<=2;

end

end

always@(negedge T) // 脱水 *** 作

begin

if(num==0&&LAMP==2)

tim<=0;

else if(num==1)

tim<=tim-1;

end

always //当设置的循环次数递减到零时报警

begin

if(baojing)

ALARM=CLK_baojing;

else

ALARM=0;

end

endmodule

基于verilog的设计是全自动洗衣机的设计，有六种不同的功能

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