求FPGA连接4*4矩阵键盘4位七段数码管(共阴)vhdl程序 跪谢！

解：

当只有语文为A时，P1=24/125

当只有数学为A时，P2=9/125

当只有外语为A时，P3=4/125

故a=P1+P2+P3=37/125

根据6/125+a+b+24/125=1

b=58/125

E=0(6/125)+1(37/125)+2(58/125)+3(24/125)

=49/25

这个有移位的指令，但用的时候可能要bit_vector的才能用（不太清楚）。还有一种方法

如a左移四位得到b，其中a、b都是8-bit的变量std_logic_vector(7 downto 0):

b := a(7)&a(7)&a(7)&a(7)&a(7 downto 4);--移走的是用a(7) 填充的

或者

b(3 downto 0) := a(7 downto 4);

b(7 downto 4) :=(others=>a(7));

源代码如下  自己把各个模块打好包  下面有个图   自己看看

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY TZKZQ IS

PORT(KEY: IN STD_LOGIC_VECTOR(1 DOWNTO 0);   --按键信号

CLK_KEY: IN STD_LOGIC;       --键盘扫描信号

MAX_DAYS:IN STD_LOGIC_VECTOR(4 DOWNTO 0);  --本月最大天数

SEC_EN,MIN_EN,HOUR_EN,DAY_EN,MON_EN,YEAR_EN,WEEK_EN:OUT STD_LOGIC; --异步并行置位使能

HOUR_CUR:IN STD_LOGIC_VECTOR(4 DOWNTO 0);

MIN_CUR,SEC_CUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0);

YEAR_CUR:IN STD_LOGIC_VECTOR(6 DOWNTO 0);

MON_CUR :IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DAY_CUR :IN STD_LOGIC_VECTOR(4 DOWNTO 0);

WEEK_CUR:IN STD_LOGIC_VECTOR(2 DOWNTO 0);

SEC,MIN:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0);

HOUR:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);

DAY :BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);

MON :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);

YEAR:BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0);

WEEK:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0));

END ENTITY TZKZQ;

ARCHITECTURE ART OF TZKZQ IS

TYPE STATETYPE IS (NORMAL,SEC_SET,MIN_SET,HOUR_SET,DAY_SET,MON_SET,

YEAR_SET,WEEK_SET);

SIGNAL MODE:STATETYPE;

BEGIN

PROCESS(KEY,CLK_KEY)

BEGIN

IF CLK_KEY'EVENT AND CLK_KEY='1' THEN

IF KEY="01" THEN

SEC_EN<='1';MIN_EN<='1';HOUR_EN<='1';

DAY_EN<='1';MON_EN<='1';YEAR_EN<='1';

WEEK_EN<='1';

CASE MODE IS

WHEN NORMAL =>  MODE<=SEC_SET;SEC<=SEC_CUR;SEC_EN<='0';

WHEN SEC_SET => MODE<=MIN_SET;MIN<=MIN_CUR;SEC_EN<='1';MIN_EN<='0';

WHEN MIN_SET => MODE<=HOUR_SET;HOUR<=HOUR_CUR;MIN_EN<='1';HOUR_EN<='0';

WHEN HOUR_SET=> MODE<=DAY_SET;DAY<=DAY_CUR;HOUR_EN<='1';DAY_EN<='0';

WHEN DAY_SET => MODE<=MON_SET;MON<=MON_CUR;DAY_EN<='1';MON_EN<='0';

WHEN MON_SET => MODE<=YEAR_SET;YEAR<=YEAR_CUR; MON_EN<='1';

YEAR_EN<='0';

WHEN YEAR_SET => MODE<=WEEK_SET;WEEK<=WEEK_CUR;YEAR_EN<='1';WEEK_EN<='0';

WHEN WEEK_SET => MODE<=NORMAL;

END CASE;

ELSIF KEY="10" THEN  --如果按下调整键，则自加

CASE MODE IS

WHEN SEC_SET => SEC_EN<='0';

--异步并行置位使能有效

IF SEC="111011" THEN SEC<="000000";

--如果秒计数到59，返回到0重新计数

ELSE SEC<=SEC+1; --否则继续计数

END IF;

WHEN MIN_SET => MIN_EN<='0';

IF MIN="111011" THEN MIN<="000000";

ELSE MIN<=MIN+1;

END IF;

WHEN HOUR_SET=> HOUR_EN<='0';

IF HOUR="11000" THEN                      HOUR<="00000";

ELSE HOUR<=HOUR+1;

END IF;

WHEN DAY_SET => DAY_EN<='0';

IF DAY=MAX_DAYS THEN DAY<="00001";

ELSE DAY<=DAY+1;

END IF;

WHEN WEEK_SET=> WEEK_EN<='0';

IF WEEK="111" THEN WEEK<="001";

ELSE WEEK<=WEEK+1;

END IF;

WHEN OTHERS=>NULL;

END CASE;

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY CNT60 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(5 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0);

CO: OUT STD_LOGIC);

END ENTITY CNT60;

ARCHITECTURE ART OF CNT60 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111011" THEN --59

NUM<="000000";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY CNT60 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(5 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0);

CO: OUT STD_LOGIC);

END ENTITY CNT60;

ARCHITECTURE ART OF CNT60 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111011" THEN --59

NUM<="000000";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY CNT24 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(4 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);

CO: OUT STD_LOGIC);

END ENTITY CNT24;

ARCHITECTURE ART OF CNT24 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="11000" THEN --24

NUM<="00000";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY CNT30 IS

PORT(LD:IN STD_LOGIC;

CLK:IN STD_LOGIC;

NIAN:IN STD_LOGIC_VECTOR(6 DOWNTO 0);

YUE :IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DATA:IN STD_LOGIC_VECTOR(4 DOWNTO 0);

NUM:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);

MAX_DAYS:OUT STD_LOGIC_VECTOR(4 DOWNTO 0);

CO:OUT STD_LOGIC);

END ENTITY CNT30;

ARCHITECTURE ART OF CNT30 IS

SIGNAL TOTAL_DAYS:STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN

PROCESS(CLK,LD) IS

VARIABLE IS_RUNNIAN:STD_LOGIC;

BEGIN

CASE NIAN IS

WHEN "0000000" => IS_RUNNIAN:='1';     --0

WHEN "0000100" => IS_RUNNIAN:='1';  --4

WHEN "0001000" => IS_RUNNIAN:='1';  --8

WHEN "0001100" => IS_RUNNIAN:='1';  --12

WHEN "0010000" => IS_RUNNIAN:='1';  --16

WHEN "0010100" => IS_RUNNIAN:='1';  --20

WHEN "0011000" => IS_RUNNIAN:='1';  --24

WHEN "0011100" => IS_RUNNIAN:='1';  --28

WHEN "0100000" => IS_RUNNIAN:='1';  --32

WHEN "0100100" => IS_RUNNIAN:='1';  --36

WHEN "0101000" => IS_RUNNIAN:='1';  --40

WHEN "0101100" => IS_RUNNIAN:='1';  --44

WHEN "0110000" => IS_RUNNIAN:='1';  --48

WHEN "0110100" => IS_RUNNIAN:='1';  --52

WHEN "0111000" => IS_RUNNIAN:='1';  --56

WHEN "0111100" => IS_RUNNIAN:='1';  --60

WHEN "1000000" => IS_RUNNIAN:='1';  --64

WHEN "1000100" => IS_RUNNIAN:='1';  --68

WHEN "1001000" => IS_RUNNIAN:='1';  --72

WHEN "1001100" => IS_RUNNIAN:='1';  --76

WHEN "1010000" => IS_RUNNIAN:='1';  --80

WHEN "1010100" => IS_RUNNIAN:='1';  --84

WHEN "1011000" => IS_RUNNIAN:='1';  --88

WHEN "1011100" => IS_RUNNIAN:='1';  --92

WHEN "1100000" => IS_RUNNIAN:='1';  --96

WHEN OTHERS    => IS_RUNNIAN:='0';

END CASE;

CASE YUE IS

WHEN "0001"  => TOTAL_DAYS<="11111"; --1

WHEN "0011"  => TOTAL_DAYS<="11111";  --3

WHEN "0101"  => TOTAL_DAYS<="11111";  --5

WHEN "0111"  => TOTAL_DAYS<="11111";  --7

WHEN "1000"  => TOTAL_DAYS<="11111";  --8

WHEN "1010"  => TOTAL_DAYS<="11111";  --10

WHEN "1100"  => TOTAL_DAYS<="11111";  --12

WHEN "0100"  => TOTAL_DAYS<="11110";  --4

WHEN "0110"  => TOTAL_DAYS<="11110";  --6

WHEN "1001"  => TOTAL_DAYS<="11110";  --9

WHEN "1011"  => TOTAL_DAYS<="11110";  --11

WHEN "0010"  =>

IF (IS_RUNNIAN='1') THEN

TOTAL_DAYS<="11101";

ELSE

TOTAL_DAYS<="11100";

END IF;

WHEN OTHERS=>NULL;

END CASE;

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

MAX_DAYS<=TOTAL_DAYS;

IF NUM=TOTAL_DAYS THEN  --99

NUM<="00001";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY CNT7 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0));

END ENTITY CNT7;

ARCHITECTURE ART OF CNT7 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111" THEN --7

NUM<="000";

ELSE

NUM<=NUM+1;

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY CNT12 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);

CO: OUT STD_LOGIC);

END ENTITY CNT12;

ARCHITECTURE ART OF CNT12 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="1100" THEN --12

NUM<="0000";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;

USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY CNT99 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(6 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0));

END ENTITY CNT99;

ARCHITECTURE ART OF CNT99 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="1100011" THEN --12

NUM<="0000000";

ELSE

NUM<=NUM+1;

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEESTD_LOGIC_1164ALL;USE IEEESTD_LOGIC_UNSIGNEDALL;

ENTITY CNT10 IS

PORT (a,b,RST,EN : IN STD_LOGIC;

CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

XOUT : STD_LOGIC_VECTOR(7 DOWNTO 0); );

END CNT10;

ARCHITECTURE behav OF CNT10 IS

PROCESS(a,b, EN) VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

IF en= '1' THEN ELSIF a'EVENT AND a='1'

THEN

CQI := CQI + 1;

ELSIF b'EVENT AND b='1'

then CQI := CQI -1;

end if；

if CQI<="0000" THEN CQI<="1001";

END if

if CQI<="1001" then CQI<="0000";

end if;

CQ<=CQI;

end Process;

PROCESS (CQ,EN)BEGIN

IF EN = ‘1’ THEN

IF CQ = “0000” THEN XOUT <= “0111111”;

ELSIF CQ = “0001” THEN XOUT <= “0000110”;

ELSIF CQ= “0010” THEN XOUT <= “1011001”;

ELSIF CQ = “0011” THEN XOUT <= “1001111”;

ELSIF CQ= “0100” THEN XOUT <= “1100110”;

ELSIF CQ= “0101” THEN XOUT <= “1101101”;

ELSIF CQ= “0110” THEN XOUT <= “1111101”;

ELSIF CQ= “0111” THEN XOUT <= “0000111”;

ELSIF CQ= “1000” THEN XOUT <= “1111111”;

ELSIF CQ= “0110” THEN XOUT <= “1101111”;

END IF;

END PROCESS;

END behav ;

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