帮忙看下这个8位全减器的VHDL代码~

一位全减器模块f_suber你真的仿真通过了吗？

注意这一句sub_out<=b AND c应为sub_out<=b OR c

在f_suber8里端口映射的时候应该用generate语句，

这样对一个几十位的减法器就不用写几十次端口映射了

一 bcd加法器。 两位BCD数加法器其事用8位的二进制数加法器就可以了，以下是我最近几天才学的 ， 呵呵， 我是EDA的 菜鸟呢

library IEEE

use IEEE.std_logic_1164.all

use ieee.numeric_std.all

entity bcdadder is

port (a: in std_logic_vector(7 downto 0)

b: in std_logic_vector(7 downto 0)

cin : in std_logic

sum : out std_logic_vector(7 downto 0)

cout : out std_logic)

end bcdadder

architecture badder of bcdadder is

signal result : unsigned (8 downto 0)

signal carry : unsigned (8 downto 0)

constant zeros: unsigned (7 downto 0) := (others=>'0')

begin

carry <=(zeros &cin )

result <=('0' &unsigned(a) )+ ('0' &unsigned(b))+carry

sum<= std_logic_vector(result(7 downto 0))

cout <= result (8)

end architecture badder

编译通过，我还没仿真测试呢

后两个晚点写给你，太晚了，虽然明天是周日

数据流描述：

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY F_suber1 IS

PORT( A,B :IN STD_LOGIC

CIN :IN STD_LOGIC

DIFF,COUT : OUT STD_LOGIC)

END

ARCHITECTURE example OF F_suber1 IS

SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0)BEGIN

S<=CIN&A&B

PROCESS(A,B,CIN)

BEGIN

CASE S IS

WHEN "000"=>DIFF<='0'COUT<='0'

WHEN "001"=>DIFF<='1'COUT<='1'

WHEN "010"=>DIFF<='1'COUT<='0'

WHEN "011"=>DIFF<='0'COUT<='0'

WHEN "100"=>DIFF<='1'COUT<='1'

WHEN "101"=>DIFF<='0'COUT<='1'

WHEN "110"=>DIFF<='0'COUT<='0'

WHEN "111"=>DIFF<='1'COUT<='1'

WHEN OTHERS=>DIFF<='X'

C

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