用vhdl设计四输入与门，两种方法

第一种方法，程序如下:

library ieee；

use ieee.std_logic_1164.all；

entity and4 is

port (a,b,c,d : in std_logic；

z : out std_logic )；

end and4；

architecture medied of and4 is

begin

z <= (a and b) and (c and d)；

end medied；

第二种方法，程序如下:

library ieee；

use ieee.std_logic_1164.all；

entity and4 is

port (a,b,c,d : in std_logic；

z : out std_logic )；

end and4；

architecture medied of and4 is

signal abcd : std_logic_vector(3 downto 0)；

begin

abcd <= a&b&c&d；

process(abcd)

begin

case abcd is

when "1111" =>Z <= '1'；

when others =>z <= '0'；

end case；

end process；

end medied；

此外还有很多写法可以实现4输入与门这个功能。

这样的程序并不复杂，建议楼主多动手写写，不能总依赖别人，自己摸索出来的东西才印象深刻。

希望你认真学习，学有所成。

LIBRARY IEEE

USE std_logic_1164.ALL

ENTITY nand_4in IS

PORT(a,b,c,d:IN std_logic

y:OUT std_logic)

END nand_4in

architecture rtl of nand_4in is

begin

y <= NOT(a AND b AND c AND d)

end rtl

ENTITY adder IS

PORT(a,b,c: IN bit

s,c0: OUT bit)

END adder

ARCHITECTURE one OF adder IS

SIGNAL y_n:bit_vector(7 DOWNTO 0)

BEGIN

decoder:PROCESS(a,b,c)

VARIABLE y:bit_vector(7 DOWNTO 0)

BEGIN

y := (OTHERS =>'1')

CASE c&b&a IS

WHEN "000" =>y(0) := '0'

WHEN "001" =>y(1) := '0'

WHEN "010" =>y(2) := '0'

WHEN "011" =>y(3) := '0'

WHEN "100" =>y(4) := '0'

WHEN "101" =>y(5) := '0'

WHEN "110" =>y(6) := '0'

WHEN "111" =>y(7) := '0'

END CASE

y_n <= y

END PROCESS

s <= NOT(y_n(1) AND y_n(2) AND y_n(4) AND y_n(7))

c0 <= NOT(y_n(3) AND y_n(5) AND y_n(6) AND y_n(7))

END one

---