VHDL 脉冲检测程序设计

VHDL不允许在一个进程中检测多个信号的边沿，只能检测某一个信号的边沿。if clk'event and clk='1'then if PUSH_IN'EVENT AND PUSH_IN='0' THEN 这种描述方式VHDL不认可。

我用quartusⅡ已编译并且仿真都对的，我写的是0亮1灭，如果实际情况与这相反，你自己倒一下。

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_SIGNED.ALL

USE IEEE.numeric_std.all

ENTITY test IS

PORT (clock: in std_logic -----clock1加48MHz的信号

row: out std_logic_vector(0 to 7))

END test

ARCHITECTURE behave OF test IS

CONSTANT fp_clka:INTEGER:=12000000 ---扫描信号频率为2Hz

SIGNAL a: INTEGER RANGE 0 TO 12000001

signal saomiao :integer range 0 to 9

SIGNAL clka: std_logic

BEGIN

PROCESS (clock)

BEGIN

IF rising_edge(clock) THEN

IF a<fp_clka then --clka

a<=a+1

clka<=clka

ELSE

a<=0

clka<= NOT clka

end if

end if

end process

process(clka)

BEGIN

IF rising_edge(clka) THEN

saomiao<=saomiao+1

if saomiao=9 then

saomiao<=0

end if

case saomiao is---'1'代表不亮,'0'代表亮

when 0 =>row<="01111111"

when 1 =>row<="10111111"

when 2 =>row<="11011111"

when 3 =>row<="11101111"

when 4 =>row<="11110111"

when 5 =>row<="11111011"

when 6 =>row<="11111101"

when 7 =>row<="11111110"

when 8 =>row<="00000000"

when others =>row<="11111111"

END CASE

END IF

end process

END behave

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