74138译码器用vhdl怎样编写

试用3

线—8

线译码器74138

扩游段大为5

线—32

线译码器。译码器74138

..

B4.1

分析8

线⑶

线编码器稿升74148

的逻辑功能，编键磨老写编码器VHDL

模块。编码器741

use IEEE.STD_LOGIC_1164.ALL

entity trans38 is

port(

A:in std_logic_vector(2 downto 0)

EN:in std_logic

Y:out std_logic_vector(7 downto 0)

)

end trans38

architecture dec_behave of trans38 is

signal sel:std_logic_vector(3 downto 0)

begin

sel<=A&EN

with sel select

Y<氏中= "00000001" when "伍败0001",

"00000010" when "0011",

"00000100" when "腔核颤0101",

"00001000" when "0111",

"00010000" when "1001",

"00100000" when "1011",

"01000000" when "1101",

"10000000" when "1111",

"XXXXXXXX" when others

end dec_behave