use ieee.std_logic_1164.all
entity paoma is
port(clk,reset:in std_logic
output:out std_logic_vector(7 downto 0))
end entity
architecture art of paoma is
begin
process(clk,reset)
variable data:std_logic_vector(7 downto 0)
begin
if reset='银源握侍1' then
data:="00000000"
elsif clk'event and clk='1' then
if data="00000000" then
data:="00000001"
else data:=data(6 downto 0)&data(7)--右到左
(data:=data(0)&data(7 downto 1))--左到右
end if
end if
output<=data
end process
end art
library ieee
use ieee.std_logic_1164.all
entity paoma is
port(clk,reset:in std_logic
output:out std_logic_vector(7 downto 0))
end entity
architecture art of paoma is
begin
process(clk,reset)
variable data:std_logic_vector(7 downto 0)
begin
if reset='1' then
data:="00000000"
elsif clk'event and clk='1' then
if data="00000000" then
data:="00011000" 中间到两边
(data:="10000001")-两边到中间
else
data:="data(6 downto 4)&data(7)&data(0)&data(3 downto 0)-从中锋皮态间到两边
(data:="data(4)&data(7 downto 5)&data(2 downto 0)&data(3))从两边到中间
end if
end fi
output<=data
end process
end art
K0:ON,则LED0亮;K1:ON,则LED0 ~ LED1亮;
K2:ON,则LED0 ~ LED2亮兄侍;
K3:ON,则LED0 ~ LED3亮;羡塌吵
K4:ON,则LED0 ~ LED4亮;
K5:ON,则LED0 ~ LED5亮;
K6:ON,则LED0 ~ LED6亮;
K7:ON,则LED0 ~ LED7亮;
其他情况,则LED0 ~ LED7全灭;
mode equ 82h 方式0,PA,PC输出,PB输入
PortA equ 8000h Port A
PortB equ 8001h Port B
PortC equ 8002h Port C
CAddr equ 8003h 控制字地址
code segment
assume cs:code
start proc near
Start:
mov al, mode
mov dx, CAddr
out dx, al 输出控制字
LOP1:
mov dx, PortB
inal, dx 读入PortB
MOV AL, 0 全0,衫梁代表都亮
MOV CX, 8
LOP2:
ROL AH, 1
JNC DISP
ROR AL, 1
LOOP LOP2
DISP:
mov dx, PortA
out dx, al 输出PortA
mov ah, 200
call delay 延时
JMP LOP1
start endp
delay proc near
push ax
mov al,0
push cx
mov cx,ax
loop $
pop cx
pop ax
ret
delay endp
code ends
end start
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