VHdl程序！！关于计数和两个时钟信号嵌套使用问题

2.微秒模块采用VHDL语言输入方式，以时钟clk，清零信号clr以及暂停信号STOP为进程敏感变量，程序如下：libraryieeeuseieee.std_logic_1164.alluseieee.std_logic_unsigned.allentityMINSECONDbisport(clk,clrm,stop:instd_logic----时钟/清零信号secm1,secm0:outstd_logic_vector(3downto0)----秒高位/低位co:outstd_logic)-------输出/进位信号endMINSECONDbarchitectureSECofMINSECONDbissignalclk1,DOUT2:std_logicbeginprocess(clk,clrm)variablecnt1,cnt0:std_logic_vector(3downto0)---计数VARIABLECOUNT2:INTEGERRANGE0TO10beginIFCLK'EVENTANDCLK='1'THENIFCOUNT2>=0ANDCOUNT2="111")thencountdaoutdaoutdaoutdaoutdaoutdaoutdaoutdaoutqqqqqqqqqq<="1101111"--显示9endcaseendprocessenddisp_are

entity counter is //定义计数器

port(clk:in Std_logic //定义计数器输入端口

rst:in std_logic

ck1:in std_logic

r:out std_logic_vector(15 downto 0)//定义计数器输出16位输出端口

)

end counter

architecture Behavioral of counter is

signal tmp:std_logic //定义临时信号

signal count:std_logic_vector(15 downto 0)

begin

process(clk,tmp,count,rst,ck1)

begin

if(rst='0') then//如果复位信号=0

r<=(others=>'0') //将r的值赋0

count<=(others=>'0') //将count的值赋0

tmp<='0' //将tmp的值赋0

elsif rising_edge(clk)then //如果是在clk的上升沿

tmp<=ck1 //将ck1的值赋给tmp

if tmp='1'and ck1='0' then//如果tmp=1并且ck1=0

r<=count//将count的值赋给r

elsif tmp='0'and ck1='1' then //如果tmp=0并且ck1=1

count<=(others=>'0') //将count的值赋0

count(0)<='1' //将count第0位的值赋1

else

count<=count+1//count+1的值赋给count

end if

end if

end process

end Behavioral

这段程序的意思就是当复位置0时，所有数据全部清0，当复位置1时，在时钟的上升沿判断tmp=1并且ck1=0就直接将count的值输出，如果tmp=0并且ck1=1 就将count的值清零，并在下一个时钟沿将count记为0000000000000001 除此以外的情况计数器count都正常+1计数

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