求一片用verilog鱼呀写的基于fpga的lcd1602显示实时数据的程序

module LCD_Driver(clk,rst,lcd_rs,lcd_en,lcd_rw,lcd_data,f0,f1,f2,d0,d1,d2,sel)

input clk,rst//时钟、复位

input [3:0] f0 //频率、占空比、档位输入

input [3:0] f1

input [3:0] f2

input [3:0] d0

input [3:0] d1

input [3:0] d2

input [3:0] sel

output lcd_rs,lcd_en,lcd_rw//指令/数据控制、片选、读写控制、背光控制

output [7:0] lcd_data//数据线

reg lcd_rs//指令/数据控制

reg [7:0] lcd_data//数据线

reg [7:0] current_state//当前状态

reg [1:0] state_counter//状态计数

reg en_temp//使能标志

reg [15:0] clk_counter//时钟计数

reg clk_en//时钟使能

//reg [7:0] ps_datain_temp

assign lcd_rw=1'b0//一直为写状态

/********************状态编码******************************/

parameter set0=8'b0000_0000,

set1=8'b0000_0001,

set2=8'b0000_0011,

set3=8'b0000_0100,

set4=8'b0000_0101,

set5=8'b0000_0110,

data1=8'b0000_1000,

data2=8'b0000_1001,

data3=8'b0000_1010,

data4=8'b0000_1011,

data5=8'b0000_1100,

data6=8'b0000_1101,

data7=8'b0000_1110,

data8=8'b0000_1111,

data9=8'b0001_0000,

data10=8'b0001_0001,

data11=8'b0001_0010,

data12=8'b0001_0011,

data13=8'b0001_0100,

data14=8'b0001_0101,

data15=8'b0001_0110,

data16=8'b0001_0111,

data17=8'b0001_1000,

data18=8'b0001_1001,

data19=8'b0001_1010,

data20=8'b0001_1011,

data21=8'b0001_1100,

data22=8'b0001_1101,

data23=8'b0001_1110,

data24=8'b0001_1111,

data25=8'b0010_0001,

data26=8'b0010_0010,

data27=8'b0010_0011,

data28=8'b0010_0100,

data29=8'b0010_0101,

data30=8'b0010_0110,

data31=8'b0010_0111,

data32=8'b0010_1000,

stop=8'b1111_1111

/**************状态转换时钟***********************/

always @(posedge clk)

begin

if(clk_counter==16'h6000)

begin

clk_counter<=16'h0

clk_en<=~clk_en

end

else

clk_counter<=clk_counter+1'b1

end

/**************状态转换**************************///

always @(posedge clk_en or negedge rst)

begin

if(!rst)

begin

current_state<=set0

end

else

begin

case (current_state)

/*********************************************************************************/

set0:begin lcd_rs<=1'b0lcd_data<=8'h38current_state<=set1end//显示模式设置

set1:begin lcd_rs<=1'b0lcd_data<=8'h0ccurrent_state<=set2end//显示开及光标设置

set2:begin lcd_rs<=1'b0lcd_data<=8'h06current_state<=set3end//显示光标移动设置

set3:begin lcd_rs<=1'b0lcd_data<=8'h01current_state<=set4end//显示清屏

set4:begin lcd_rs<=1'b0lcd_data<=8'h80current_state<=data1end//设置第一行地址

/***********************************************************************************/

data1:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data2end//显示第1个字符

data2:begin lcd_rs<=1'b1lcd_data<="F"current_state<=data3end//显示第2个字符

data3:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data4end//显示第3个字符

data4:begin lcd_rs<=1'b1lcd_data<="="current_state<=data5end//显示第4个字符

data5:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data6end//显示第5个字符

data6:begin lcd_rs<=1'b1lcd_data<=f0+"0"current_state<=data7end//显示第6个字符

data7:begin lcd_rs<=1'b1lcd_data<=f1+"0"current_state<=data8end//显示第7个字符

data8:begin lcd_rs<=1'b1lcd_data<=f2+"0"current_state<=data9end//显示第8个字符

data9:begin lcd_rs<=1'b1lcd_data<="x"current_state<=data10end//显示第1个字符

data10:begin lcd_rs<=1'b1if(sel[3])lcd_data<="1"else lcd_data<="0"current_state<=data11end//显示第2个字符

data11:begin lcd_rs<=1'b1if(sel[2])lcd_data<="1"else lcd_data<="0"current_state<=data12end//显示第3个字符

data12:begin lcd_rs<=1'b1if(sel[1])lcd_data<="1"else lcd_data<="0"current_state<=data13end//显示第4个字符

data13:begin lcd_rs<=1'b1if(sel[0])lcd_data<="1"else lcd_data<="0"current_state<=data14end//显示第5个字符

data14:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data15end//显示第6个字符

data15:begin lcd_rs<=1'b1lcd_data<="H"current_state<=data16end//显示第7个字符

data16:begin lcd_rs<=1'b1lcd_data<="Z"current_state<=set5end//显示第8个字符

set5:begin lcd_rs<=1'b0lcd_data<=8'hc0current_state<=data17end//设置第2行地址

data17:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data18end//显示第1个字符

data18:begin lcd_rs<=1'b1lcd_data<="D"current_state<=data19end//显示第2个字符

data19:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data20end//显示第3个字符

data20:begin lcd_rs<=1'b1lcd_data<="="current_state<=data21end//显示第4个字符

data21:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data22end//显示第5个字符

data22:begin lcd_rs<=1'b1lcd_data<=d0+"0"current_state<=data23end//显示第6个字符

data23:begin lcd_rs<=1'b1lcd_data<=d1+"0"current_state<=data24end//显示第7个字符

data24:begin lcd_rs<=1'b1lcd_data<=d2+"0"current_state<=data25end//显示第8个字符

data25:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data26end//显示第二个字符

data26:begin lcd_rs<=1'b1lcd_data<="%"current_state<=data27end//显示第四个字符

data27:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data28end//显示第五个字符

data28:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data29end//显示第六个字符

data29:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data30end//显示第七个字符

data30:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data31end//显示第八个字符

data31:begin lcd_rs<=1'b1lcd_data<=" "current_state<=data32end//显示第九个字符

data32:begin lcd_rs<=1'b1lcd_data<=" "current_state<=stopend//显示第九个字符

/*********************************************************************************/

stop:begin //控制指令与数据写入的次数

lcd_rs<=1'b0

lcd_data<=8'b0000_0000

if(state_counter!=2'b10)

begin

en_temp<=1'b0

current_state<=set4

state_counter<=state_counter+1'b1

end

else

begin

current_state<=set4

en_temp<=1'b0//最后数据写入完成后将lcd_en线拉高

end

end

default: current_state<=set0

endcase

end

end

assign lcd_en=clk_en|en_temp//lcd_en为‘1’有效

endmodule

写的PWM，如果实时显示就要状态机一直循环，并且给模块定义一个数据输入变量

//www.21eda.com

//开发板型号:A-C8V4

//深圳市21EDA电子

//利用Verilog驱动LCD12864

//本实验是用LCD12864显示汉字。（LCD带字库）

//视频教程适合我们21EDA电子的所有学习板）

module LCD12864 (clk, rs, rw, en,dat)

input clk //系统时钟输入50M

output [7:0] dat //LCD的8位数据口

output rs,rw,en //LCD的控制脚

reg e

reg [7:0] dat

reg rs

reg [15:0] counter

reg [6:0] current,next

reg clkr

reg [1:0] cnt

//定义的一些状态机。

parameter set0=6'h0

parameter set1=6'h1

parameter set2=6'h2

parameter set3=6'h3

parameter set4=6'h4

parameter set5=6'h5

parameter set6=6'h6

parameter dat0=6'h7

parameter dat1=6'h8

parameter dat2=6'h9

parameter dat3=6'hA

parameter dat4=6'hB

parameter dat5=6'hC

parameter dat6=6'hD

parameter dat7=6'hE

parameter dat8=6'hF

parameter dat9=6'h10

parameter dat10=6'h12

parameter dat11=6'h13

parameter dat12=6'h14

parameter dat13=6'h15

parameter dat14=6'h16

parameter dat15=6'h17

parameter dat16=6'h18

parameter dat17=6'h19

parameter dat18=6'h1A

parameter dat19=6'h1B

parameter dat20=6'h1C

parameter dat21=6'h1D

parameter dat22=6'h1E

parameter dat23=6'h1F

parameter dat24=6'h20

parameter dat25=6'h21

parameter dat26=6'h22

parameter dat27=6'h23

parameter dat28=6'h24

parameter dat29=6'h25

parameter dat30=6'h26

parameter dat31=6'h27

parameter dat32=6'h28

parameter dat33=6'h29

parameter dat34=6'h2A

parameter dat35=6'h2B

parameter dat36=6'h2C

parameter dat37=6'h2E

parameter dat38=6'h2F

parameter dat39=6'h30

parameter dat40=6'h31

parameter dat41=6'h32

parameter dat42=6'h33

parameter dat43=6'h34

/////////////////////////////////////////////

parameter nul=6'h35

always @(posedge clk) //da de shi zhong pinlv

begin

counter=counter+1

if(counter==16'h000f)

clkr=~clkr

end

////////////////////////////////////////////////

always @(posedge clkr)

begin

current=next

case(current)

set0: begin rs<=0dat<=8'h31next<=set1end //*设置8位格式,*

set1: begin rs<=0dat<=8'h0Cnext<=set2end //*整体显示,关光标,不闪烁*/

set2: begin rs<=0dat<=8'h06next<=set3end //*设定输入方式,增量不移位*/

set3: begin rs<=0dat<=8'h01next<=dat0end //*清除显示*/

dat0: begin rs<=1dat<=8'hc9next<=dat1end //显示第一行

dat1: begin rs<=1dat<=8'heenext<=dat2end

//上面是‘深’字的ACSII码值 C9EE

dat2: begin rs<=1dat<=8'hdbnext<=dat3end

dat3: begin rs<=1dat<=8'hdanext<=dat4end

//上面是‘圳’字的ACSII码值DBDA

dat4: begin rs<=1dat<=8'hcanext<=dat5end

dat5: begin rs<=1dat<=8'hd0next<=dat6end

//上面是‘市’字的ACSII码值CAD0

dat6: begin rs<=1dat<="2"next<=dat7end

dat7: begin rs<=1dat<="1"next<=dat8end

dat8: begin rs<=1dat<="E"next<=dat9end

dat9: begin rs<=1dat<="D"next<= dat10 end

dat10: begin rs<=1dat<=8'hB5next<=dat11end

dat11: begin rs<=1dat<=8'hE7next<=dat12end

//上面是‘电’字的ACSII码值B5E7

dat12: begin rs<=1dat<=8'hd7next<=dat13end

dat13: begin rs<=1dat<=8'hd3next<=set4end

//上面是‘子’字的ACSII码值D7D3

set4: begin rs<=0dat<=8'h90next<=dat14end //显示第二行

dat14: begin rs<=1dat<=8'hD0next<=dat15end

dat15: begin rs<=1dat<=8'hCDnext<=dat16end

//上面是‘型’字的ACSII码值D0CD

dat16: begin rs<=1dat<=8'hBAnext<=dat17end

dat17: begin rs<=1dat<=8'hC5next<=dat18end

//上面是‘号’字的ACSII码值BAC5

dat18: begin rs<=1dat<=":"next<=dat19end

dat19: begin rs<=1dat<="A"next<=dat20end

dat20: begin rs<=1dat<="-"next<=dat21end

dat21: begin rs<=1dat<="C"next<=dat22end

dat22: begin rs<=1dat<="8"next<=dat23end

dat23: begin rs<=1dat<="V"next<=dat24 end

dat24: begin rs<=1dat<="4"next<=dat25end

dat25: begin rs<=1dat<=" "next<=dat26end

dat26: begin rs<=1dat<=8'hbfnext<=dat27end

dat27: begin rs<=1dat<=8'hd8next<=dat28end

//上面是‘控’字的ACSII码值BFD8

dat28: begin rs<=1dat<=8'hd6next<=dat29end

dat29: begin rs<=1dat<=8'hc6next<=set5 end

//上面是‘制’字的ACSII码值D6C6

set5: begin rs<=0dat<=8'h88next<=dat30end //显示第三行

dat30: begin rs<=1dat<="L"next<=dat31end

dat31: begin rs<=1dat<="C"next<=dat32end

dat32: begin rs<=1dat<="D"next<=dat33end

dat33: begin rs<=1dat<="1"next<=dat34end

dat34: begin rs<=1dat<="2"next<=dat35 end

dat35: begin rs<=1dat<="8"next<=dat36 end

dat36: begin rs<=1dat<="6"next<=dat37 end

dat37: begin rs<=1dat<="4"next<=set6 end

set6: begin rs<=0dat<=8'h9Cnext<=dat38end //显示第四行

dat38: begin rs<=1dat<="G"next<=dat39end

dat39: begin rs<=1dat<="O"next<=dat40end

dat40: begin rs<=1dat<="O"next<=dat41end

dat41: begin rs<=1dat<="D"next<=dat42 end

dat42: begin rs<=1dat<="!"next<=dat43 end

dat43: begin rs<=1dat<="!"next<=nul end

nul: begin rs<=0 dat<=8'h00 // 把液晶的E 脚 拉高

if(cnt!=2'h2)

begin

e<=0next<=set0cnt<=cnt+1

end

else

begin next<=nule<=1

end

end

default: next=set0

endcase

end

assign en=clkr|e

assign rw=0

endmodule

verilog程序，自己翻译成VHDL吧

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