用FPGA怎样实现将模拟量转换成数字量？

fpga不能直接实现模拟量转换成数字量，这一功能要由AD转换芯片完成，FPGA可以将AD芯片转换的结果读出来，即是模拟量转换成的数字量的值。

FPGA是一中数森羡字处理芯片，是不能羡肆与模拟量相连的，更不能处理模拟量。

你这是对FPGA这一芯片不了解，或者说对数字电路概念研究不深，找相关书籍仔细理解下就好了。我一开始也是这样的。

祝进步！兄春轿

FPGA是不能实现DA转换的，它内部处理的都是数字信号，不能输出模拟信号。一般是用FPGA控制系统工作流程，产生控制信号，DSP输出数字信号处理后得到的数字信号，经专门的DA芯片，如PCM1798、1794、AD1955、CS4398、AK4396、AK4399等等，FPGA只能实现特定类型的脉冲，手磨如下:

library

ieee

use

ieee.std_logic_1164.all

use

ieee.std_logic_arith.all

use

ieee.std_logic_unsigned.all

entity

dac_ds

is

port(reset

:in

std_logic

clk

:in

std_logic

din

:in

std_logic_vector(7

downto

0)--Signed

integer

dout

:out

std_logic)

end

dac_ds

architecture

arch_dac_ds

of

dac_ds

is

signal

error

:std_logic_vector(9

downto

0)--Error

accumulator

is

2

bits

larger

constant

zeros:std_logic_vector(7

downto

0):=(others=>'0')

begin

process(reset,clk,din)

variable

val

:std_logic_vector(9

downto

0)

begin

if

reset='1'then

error<=(others=>'0')

dout<='0'

elsif

clk'event

and

clk='1'

then

--val:=din+errordin

is

sign

extended

to

nbits+2

val:=(din(din'high)&din(din'high)&din)+error

if

val(val'high)='0'then

dout<毕毁斗='1'

error<=val+("11"&

zeros)

else

dout<='0'

error<=val+("01"余做&zeros)

end

if

end

if

end

process

end

arch_dac_ds

思路:

六位二进制数->2位BCD->七段译码器转为数码管显示

附一个 8位BCD码转换程序供你参考(y0~y7是8位BCD码输出(每个4位),din是二进制输入),位数宽度自己改吧,七段译码器也附上了,这孝薯个不用改了,连线上就能用了.

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_unsigned.all

use ieee.std_logic_arith.all

entity B_BCD is

port(clk:in std_logic

din:in std_logic_vector(26 downto 0)

y0,y1,y2,y3,y4,y5,y6,y7:out std_logic_vector(3 downto 0))

end B_BCD

architecture behav of B_BCD is

type state is (s0,s1,s2)

signal present_state:state

signal mid_in:std_logic_vector(26 downto 0)

signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(3 downto 0)

begin

process(clk)is

begin

if clk'event and clk='1' then

mid_in<=din

present_state<=s0

case (present_state) is

when s0=>

d0<="0000"d1<="0000"d2<="0000"d3<="0000"d4<="0000"d5<="0000"d6<="0000"d7<="0000"

present_state<=s1

when s1=>

if mid_in>="100110001001011010000000" then mid_in<=mid_in-"100110001001011010000000"

d7<=d7+1

present_state<=s1

elsif mid_in>="000011110100001001000000" then mid_in<者慎逗=mid_in-"000011110100001001000000"

d6<=d6+1

present_state<=s1

elsif mid_in>="000000011000011010100000" then mid_in<=mid_in-"000000011000011010100000"

d5<=d5+1

present_state<=s1

elsif mid_in>="000000000010011100010000" then mid_in<=mid_in-"000000000010011100010000"首卖

d4<=d4+1

present_state<=s1

elsif mid_in>="000000000000001111101000" then mid_in<=mid_in-"000000000000001111101000"

d3<=d3+1

present_state<=s1

elsif mid_in>="000000000000000001100100" then mid_in<=mid_in-"000000000000000001100100"

d2<=d2+1

present_state<=s1

elsif mid_in>="000000000000000000001010" then mid_in<=mid_in-"000000000000000000001010"

d1<=d1+1

present_state<=s1

elsif mid_in>="000000000000000000000001" then

mid_in<=mid_in-"000000000000000000000001"

d0<=d0+1

present_state<=s1

else

present_state<=s2

end if

when s2=>

y0<=d0y1<=d1y2<=d2y3<=d3y4<=d4y5<=d5y6<=d6y7<=d7

present_state<=s0

when others=>

present_state<=s0

end case

end if

end process

end behav

--七段译码器

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

ENTITY decoder_7_part IS

PORT(i3,i2,i1,i0:IN STD_LOGIC

a,b,c,d,e,f,g:OUT STD_LOGIC)

END decoder_7_part

ARCHITECTURE rtl OF decoder_7_part IS

SIGNAL indata:STD_LOGIC_VECTOR(3 DOWNTO 0)

signal outdata:STD_LOGIC_VECTOR(6 DOWNTO 0)

BEGIN

process(indata)

begin

indata<=i3&i2&i1&i0

CASE indata IS

WHEN "0000"=>outdata<="1111110"

WHEN "0001"=>outdata<="0110000"

WHEN "0010"=>outdata<="1101101"

WHEN "0011"=>outdata<="1111001"

WHEN "0100"=>outdata<="0110011"

WHEN "0101"=>outdata<="1011011"

WHEN "0110"=>outdata<="0011111"

WHEN "0111"=>outdata<="1110000"

WHEN "1000"=>outdata<="1111111"

WHEN "1001"=>outdata<="1111011"

when others=>outdata<="0000000"

END CASE

a<=outdata(0)

b<=outdata(1)

c<=outdata(2)

d<=outdata(3)

e<=outdata(4)

f<=outdata(5)

g<=outdata(6)

END process

end

---