程序如下:
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity xuan21 is
Port ( alarm,a,b: in std_logic
y:out std_logic)
end xuan21
architecture one of xuan21 is
begin
process(alarm,a,b)
begin
if alarm='0' then y<=aelse y<=b
end if
end process
end one
仿真波形如下图12:
图12
(2)三位二选一:
模块图如图13。用以进行正常计时时间与闹铃时间显示的选择,alarm输入为按键。猜春当alarm按键未曾按下时二选一选洞好择器会选择输出显示正常的计时结果,否则当alarm按键按下时选择器将选择输出显示闹铃时间显示。
图13
程序如下:
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity x213 is
Port ( alarm : in std_logic
y:out std_logic_vector(3 downto 0)
a,b: in std_logic_vector(3 downto 0))
end x213
architecture one of x213 is
begin
process(alarm,a,b)
begin
if alarm='0' then y<=aelse y<=b
end if
end process
end one
仿真结果如下图14:
图纳兆铅14
8、整点报时及闹时:
模块图如图15。在59分51秒、53秒、55秒、57秒给扬声器赋以低音512Hz信号,在59分59秒给扬声器赋以高音1024Hz信号,音响持续1秒钟,在1024Hz音响结束时刻为整点。当系统时间与闹铃时间相同时给扬声器赋以高音1024Hz信号。闹时时间为一分钟。
图15
程序如下:
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity voice is
Port ( hou1,huo0,min1,min0,sec1,sec0,hh,hl,mh,ml: std_logic_vector(3 downto 0)
in_1000,in_500:in std_logic
q : out std_logic)
end voice
architecture one of voice is
begin
process(min1,min0,sec1,sec0)
begin
if min1="0101" and min0="1001" and sec1="0101" then
if sec0="0001" or sec0="0011" or sec0="0101" or sec0="0111"
then q<=in_500
elsif sec1="0101" and sec0="1001" then q<=in_1000
else q<='0'
end if
else q<='0'
end if
if min1=mh and min0=ml and hou1=hh and huo0=hl then
q<=in_1000
end if
end process
end one
仿真波形如下图16
图16
9、顶层原理图:
三、感想
通过这次设计,既复习了以前所学的知识,也进一步加深了对EDA的了解,让我对它有了更加浓厚的兴趣。特别是当每一个子模块编写调试成功时,心里特别的开心。但是在画顶层原理图时,遇到了不少问题,最大的问题就是根本没有把各个模块的VHD文件以及生成的器件都全部放在顶层文件的文件夹内,还有就是程序设计的时候考虑的不够全面,没有联系着各个模式以及实验板的情况来编写程序,以至于多考虑编写了译码电路而浪费了很多时间。在波形仿真时,也遇到了一点困难,想要的结果不能在波形上得到正确的显示
:在分频模块中,设定输入的时钟信号后,却只有二分频的结果,其余三个分频始终没反应。后来,在数十次的调试之后,才发现是因为规定的信号量范围太大且信号的初始值随机,从而不能得到所要的结果。还有的仿真图根本就不出波形,怎么调节都不管用,后来才知道原来是路径不正确,路径中不可以有汉字。真是细节决定成败啊!总的来说,这次设计的数字钟还是比较成功的,有点小小的成就感,终于觉得平时所学的知识有了实用的价值,达到了理论与实际相结合的目的,不仅学到了不少知识,而且锻炼了自己的能力,使自己对以后的路有了更加清楚的认识,同时,对未来有了更多的信心。
四、参考资料:
1、潘松,王国栋,VHDL实用教程〔M〕.成都:电子科技大学出版社,2000.(1)
2、崔建明主编,电工电子EDA仿真技术北京:高等教育出版社,2004
3、李衍编著,EDA技术入门与提高王行西安:西安电子科技大学出版社,2005
4、侯继红,李向东主编,EDA实用技术教程北京:中国电力出版社,2004
5、沈明山编著,EDA技术及可编程器件应用实训北京:科学出版社,2004
6、侯伯亨等,VHDL硬件描述语言与数字逻辑电路设计西安: 西安电子科技大学出版社,1997
7、辛春艳编著,VHDL硬件描述语言北京:国防工业出版社,2002 就这些
交通尘首皮灯VHDL程序LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
PACKaGE traffic1 IS --TYPE color IS (green,yellow,red,unknown)
TYPE state IS (highway_green,
highway_yellow,
general_green,
general_yellow)
END traffic1
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE WORK.traffic1.ALL
ENTITY traffic IS
--GENERIC(time_long:TIME
PORT(car_on_general:IN BOOLEAN
clk:in std_logic
highway_light:OUT std_logic_vector(2 downto 0)
general_light:OUT std_logic_vector(2 downto 0))
END traffic
ARCHITECTURE rtl OF traffic IS
SIGNAL present_state:state
SIGNAL next_state:state
SIGNAL time_out_long:boolean:=FALSE
SIGNAL time_out_short:boolean:=FALSE
SIGNAL start_timer:boolean:=FALSE
BEGIN
contron:PROCESS(present_state ,car_on_general,time_out_long,time_out_short)
begin
CASE present_state IS
WHEN highway_green=>
if car_on_general and time_out_long then
next_state<=highway_yellow
end if
WHEN highway_yellow=>
if time_out_short then
next_state<=general_green
end if
WHEN general_green=>
if not car_on_general or time_out_long then
next_state<=general_yellow
end if
WHEN general_yellow=>
if time_out_short then
next_state<=highway_green
end if
END CASE
END PROCESS
start:PROCESS(clk)
BEGIN
IF (clk'event and clk='1') THEN
present_state<=next_state
END IF
END PROCESS
out_put:PROCESS(present_state)
BEGIN
start_timer<= not start_timer
CASE present_state IS
WHEN highway_green=>
highway_light<= "100"
general_light<= "001"
WHEN highway_yellow=>
highway_light<= "010"
general_light<= "001"
WHEN general_green=>
general_light<= "100"
highway_light<="芹正001"
WHEN general_yellow=>
general_light<="010"
highway_light<="派差001"
END CASE
END PROCESS
time:PROCESS(start_timer)
BEGIN
time_out_long<= FALSE
time_out_long<= TRUE AFTER 1000 sec
time_out_short<= FALSE
time_out_short<= TRUE AFTER 2 sec
END PROCESS
END rtl
另一个比较高级的:
http://www.eccn.com/xsj06/xsj071131w.asp
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