vhdl语言的多个模块如何组成一个程序

多个模块之间的信号通过port map的方式，实现模块之间的信号互联。比如说你的顶层模块是top，下面有A和B，A是输入模块，B是输出模块，A和B之间有个控制信号start相连。\x0d\entity top is port(aaa: in std_logic;\x0d\ bbb: out std_logic );\x0d\aaa是它的输入，bbb是他的输出。它内部有两个模块A和B\x0d\先定义一个连线信号signal start： std_logic;\x0d\component A;声明A 简单写了，详见VHDL语法书\x0d\component B;声明B\x0d\dut_a: A port map(aaa => aaa, --aaa连到top的aaa\x0d\ start => start); --start连到B的start\x0d\dut_b: B port map(start => start, --start连到A的start\x0d\ bbb => bbb); --bbb连到top的bbb。\x0d\找本书看看吧，简单的很。

第一种方法，程序如下:

library ieee；

use ieeestd_logic_1164all；

entity and4 is

port (a,b,c,d : in std_logic；

z : out std_logic )；

end and4；

architecture medied of and4 is

begin

z <= (a and b) and (c and d)；

end medied；

第二种方法，程序如下:

library ieee；

use ieeestd_logic_1164all；

entity and4 is

port (a,b,c,d : in std_logic；

z : out std_logic )；

end and4；

architecture medied of and4 is

signal abcd : std_logic_vector(3 downto 0)；

begin

abcd <= a&b&c&d；

process(abcd)

begin

case abcd is

when "1111" => Z <= '1'；

when others => z <= '0'；

end case；

end process；

end medied；

此外还有很多写法可以实现4输入与门这个功能。

这样的程序并不复杂，建议楼主多动手写写，不能总依赖别人，自己摸索出来的东西才印象深刻。

希望你认真学习，学有所成。

----注： 本工程为用structure方法实现多路选择

----Date: 2013-09-25-

----Author： Mabs

-----------------------------------------------------------------------------------

-------与门------------------------------------------------------------------------

library ieee;

use ieeestd_logic_1164all;

entity and_ab is

port(

A,B : in std_logic;

C : out std_logic

);

architecture bhv of and_ab is

begin

C <= B and A;

end bhv;

-----------------------------------------------------------------------------------

-------或门------------------------------------------------------------------------

library ieee;

use ieeestd_logic_1164all;

entity or_ab is

port(

A,B : in std_logic;

C : out std_logic

);

architecture bhv of or_ab is

begin

C <= B or A;

end bhv;

-----------------------------------------------------------------------------------

-------非门------------------------------------------------------------------------

library ieee;

use ieeestd_logic_1164all;

entity not_a is

port(

A : in std_logic;

C : out std_logic

);

architecture bhv of not_a is

begin

C <= not A;

end bhv;

-----------------------------------------------------------------------------------

-------3input与门------------------------------------------------------------------------

library ieee;

use ieeestd_logic_1164all;

entity and3_abc is

port(

A,B,C : in std_logic;

D : out std_logic

);

architecture bhv of and3_abc is

component and_ab is

port(

A,B : in std_logic;

C : out std_logic

);

end component;

signal tmp : std_logic;

begin

u1_and: and_ab

port map

( A => A,

B => B,

C => tmp

);

u2_and: and_ab

port map

( A => C,

B => tmp,

C => D

);

end bhv;

-----------------------------------------------------------------------------------

-------7input或门------------------------------------------------------------------------

library ieee;

use ieeestd_logic_1164all;

entity or7_abc is

port(

A,B,C,D,E,F,G : in std_logic;

H : out std_logic

);

architecture bhv of or7_abc is

component or_ab is

port(

A,B : in std_logic;

C : out std_logic

);

end component;

signal tmpAB,tmpABC,tmpABCD,tmpABCDE,tmpABCDEF : std_logic;

begin

u1_or: or_ab

port map

( A => A,

B => B,

C => tmpAB

);

u2_or: or_ab

port map

( A => C,

B => tmpAB,

C => tmpABC

);

u3_or: or_ab

port map

( A => D,

B => tmpABC,

C => tmpABCD

);

u4_or: or_ab

port map

( A => E,

B => tmpABCD,

C => tmpABCDE

);

u5_or: or_ab

port map

( A => F,

B => tmpABCDE,

C => tmpABCCDEF

);

u6_or: or_ab

port map

( A => G,

B => tmpABCDEF,

C => H

);

end bhv;

-----------------------------------------------------------------------------------

----main-------------------------------------------------------------------------------

library ieee;

use ieeestd_logic_1164all;

use ieeestd_logic_unsignedall;

use ieeestd_logic_arithall;

use workpkg;

entity 7sel_to1 is

port(

Din1,Din2,Din3,Din4,Din5,Din6,Din7 : in std_logic_vector(4 downto 0);

S1,S2,S3 : in std_logic;

Dout : out std_logic_vector(4 downto 0)

);

architecture bhv of 7sel_to1 is

component and_ab is

port(

A,B : in std_logic;

C : out std_logic

);

end component;

component or_ab is

port(

A,B : in std_logic;

C : out std_logic

);

end component;

component not_a is

port(

A : in std_logic;

C : out std_logic

);

end component;

component and3_abc is

port(

A,B,C : in std_logic;

D : out std_logic

);

end component;

component or7_abc is

port(

A,B,C,D,E,F,G : in std_logic;

H : out std_logic

);

signal tmp1,tmp2,tmp3,tmp4,tmp5,tmp6,tmp7 : std_logic_vector(4 downto 0);

signal nS1,nS2,nS3 : std_logic;

signal sel1,sel2,sel3,sel4,sel5,sel6,sel7 : std_logic;

begin

---not--------------

u1_not_S1: not_a

port map(

A=>S1,

C=>nS1

);

u2_not_S2: not_a

port map(

A=>S2,

C=>nS2

);

u3_not_S3: not_a

port map(

A=>S3,

C=>nS3

);

---3and---------------

u1_and_nS1nS2nS3: and3_abc

port map(

A=>nS1,

B=>nS2,

C=>nS3,

D=>sel1

);

u2_and_nS1nS2S3: and3_abc

port map(

A=>nS1,

B=>nS2,

C=>S3,

D=>sel2

);

u3_and_nS1S2nS3: and3_abc

port map(

A=>nS1,

B=>S2,

C=>nS3,

D=>sel3

);

u4_and_nS1S2S3: and3_abc

port map(

A=>nS1,

B=>S2,

C=>S3,

D=>sel4

);

u5_and_S1nS2nS3: and3_abc

port map(

A=>S1,

B=>nS2,

C=>nS3,

D=>sel5

);

u6_and_S1nS2S3: and3_abc

port map(

A=>S1,

B=>nS2,

C=>S3,

D=>sel6

);

u7_and_S1S2nS3: and3_abc

port map(

A=>S1,

B=>S2,

C=>nS3,

D=>sel7

);

------------------------

---and0---------------------

u1_and0: and_ab

port map

( A => sel1,

B => Din1(0),

C => tmp1(0)

);

u2_and0: and_ab

port map

( A => sel2,

B => Din2(0),

C => tmp2(0)

);

u3_and0: and_ab

port map

( A => sel3,

B => Din3(0),

C => tmp3(0)

);

u4_and0: and_ab

port map

( A => sel4,

B => Din4(0),

C => tmp4(0)

);

u5_and0: and_ab

port map

( A => sel5,

B => Din5(0),

C => tmp5(0)

);

u6_and0: and_ab

port map

( A => sel6,

B => Din6(0),

C => tmp6(0)

);

u7_and0: and_ab

port map

( A => sel7,

B => Din7(0),

C => tmp7(0)

);

------------------------

-----1-------------------

u1_and1: and_ab

port map

( A => sel1,

B => Din1(1),

C => tmp1(1)

);

u2_and1: and_ab

port map

( A => sel2,

B => Din2(1),

C => tmp2(1)

);

u3_and1: and_ab

port map

( A => sel3,

B => Din3(1),

C => tmp3(1)

);

u4_and1: and_ab

port map

( A => sel4,

B => Din4(1),

C => tmp4(1)

);

u5_and1: and_ab

port map

( A => sel5,

B => Din5(1),

C => tmp5(1)

);

u6_and1: and_ab

port map

( A => sel6,

B => Din6(1),

C => tmp6(1)

);

u7_and1: and_ab

port map

( A => sel7,

B => Din7(1),

C => tmp7(1)

);

------------------------

----2--------------------

u1_and2: and_ab

port map

( A => sel1,

B => Din1(2),

C => tmp1(2)

);

u2_and2: and_ab

port map

( A => sel2,

B => Din2(2),

C => tmp2(2)

);

u3_and2: and_ab

port map

( A => sel3,

B => Din3(2),

C => tmp3(2)

);

u4_and2: and_ab

port map

( A => sel4,

B => Din4(2),

C => tmp4(2)

);

u5_and2: and_ab

port map

( A => sel5,

B => Din5(2),

C => tmp5(2)

);

u6_and2: and_ab

port map

( A => sel6,

B => Din6(2),

C => tmp6(2)

);

u7_and2: and_ab

port map

( A => sel7,

B => Din7(2),

C => tmp7(2)

);

------------------------

----3--------------------

u1_and3: and_ab

port map

( A => sel1,

B => Din1(3),

C => tmp1(3)

);

u2_and3: and_ab

port map

( A => sel2,

B => Din2(3),

C => tmp2(3)

);

u3_and3: and_ab

port map

( A => sel3,

B => Din3(3),

C => tmp3(3)

);

u4_and3: and_ab

port map

( A => sel4,

B => Din4(3),

C => tmp4(3)

);

u5_and3: and_ab

port map

( A => sel5,

B => Din5(3),

C => tmp5(3)

);

u6_and3: and_ab

port map

( A => sel6,

B => Din6(3),

C => tmp6(3)

);

u7_and3: and_ab

port map

( A => sel7,

B => Din7(3),

C => tmp7(3)

);

------------------------

----4--------------------

u1_and4: and_ab

port map

( A => sel1,

B => Din1(4),

C => tmp1(4)

);

u2_and4: and_ab

port map

( A => sel2,

B => Din2(4),

C => tmp2(4)

);

u3_and4: and_ab

port map

( A => sel3,

B => Din3(4),

C => tmp3(4)

);

u4_and4: and_ab

port map

( A => sel4,

B => Din4(4),

C => tmp4(4)

);

u5_and4: and_ab

port map

( A => sel5,

B => Din5(4),

C => tmp5(4)

);

u6_and4: and_ab

port map

( A => sel6,

B => Din6(4),

C => tmp6(4)

);

u7_and4: and_ab

port map

( A => sel7,

B => Din7(4),

C => tmp7(4)

);

------------------------

--===========================

u1_or: or7_abc

port map

( A => tmp1(0),

B => tmp2(0),

C => tmp3(0),

D => tmp4(0),

E => tmp5(0),

F => tmp6(0),

G => tmp7(0),

H => Dout(0)

);

u2_or: or7_abc

port map

( A => tmp1(1),

B => tmp2(1),

C => tmp3(1),

D => tmp4(1),

E => tmp5(1),

F => tmp6(1),

G => tmp7(1),

H => Dout(1)

);

u3_or: or7_abc

port map

( A => tmp1(2),

B => tmp2(2),

C => tmp3(2),

D => tmp4(2),

E => tmp5(2),

F => tmp6(2),

G => tmp7(2),

H => Dout(2)

);

u4_or: or7_abc

port map

( A => tmp1(3),

B => tmp2(3),

C => tmp3(3),

D => tmp4(3),

E => tmp5(3),

F => tmp6(3),

G => tmp7(3),

H => Dout(3)

);

u5_or: or7_abc

port map

( A => tmp1(4),

B => tmp2(4),

C => tmp3(4),

D => tmp4(4),

E => tmp5(4),

F => tmp6(4),

G => tmp7(4),

H => Dout(4)

);

--=============================

end bhv;

library ieee;

use ieeestd_logic_1164all

entity mux2_1 is

port(a,b,s:in std_logic;

y:out std_logic );

end mux2_1;

architecture bhv of mux2_1 is

begin

if s='1' then y<=a;

elsif s='0' then y<=b;

else y<='Z';

end if;

end bhv;

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