OverviewThe DS2151, DS2152, DS21352, DS21552 and DS2155 single-chip transceivers incorporate all the key performance indications that are required by ANSI T1.231-1997 (originally dated 1993), entitled "Digital Hierarchy–Layer 1 In-Service Digital Transmission Performance Monitoring."
Table 1 lists all important parameters and where they are located within the DS2151, DS2152, DS21352, DS21552, and DS2155. These T1 transceivers do the raw collection of the data. The devices rely on the external host to accumulate the parameters and create the higher order statistics such as errored seconds, severely errored seconds, LOS seconds, and so on. The one-second timer within these T1 transceivers is ideal for timing these higher order statistics.
Table 1. DS2151 and DS2152 Parameters
- RIR1.0
- Path Code Violation Count Registers in D4 framing mode with RCR2.0 = 0
- Multiframes Out-of-Sync Count Registers in ESF mode with RCR2.0 = 1
RIR2.3 on transmit side
(RCR1.4 and RCR1.5 are used to set the criteria.)
Note 1: The DS2151 and DS2152 only count each excessive zero string once. For example, a string of 48 consecutive zeros would only increment the line code violation count registers once, not multiple times.
Note 2: Via the RCR2.1 bit, the user has the choice in the D4 framing mode of counting errors in just the Ft-bit pattern or in both the Ft-bit and the Fs-bit patterns.
Note 3: In the D4 framing mode, the SEFE bit (RIR1.2) only counts errors in the Ft-bit pattern; in the ESF framing mode, only errors in the FPS pattern are counted.
Table 2. DS21352 and DS21552 Parameters
- RIR1.0
- Path Code Violation Count Registers in D4 framing mode with RCR2.0 = 0
- Multiframes Out-of-Sync Count Registers in ESF mode with RCR2.0 = 1
RIR2.3 on transmit side
(RCR1.4 and RCR1.5 are used to set the criteria)
Note 1: Table 3 shows the counting arrangements for the Line Code Violation Count Registers on the DS21352 and the DS21552.
Note 2: Via the RCR2.1 bit, the user has the choice in the D4 framing mode of counting errors in just the Ft bit pattern or in both the Ft and Fs bit patterns.
Note 3: In the D4 framing mode, the SEFE bit (RIR1.2) only counts errors in the Ft pattern; in the ESF framing mode, only errors in the FPS pattern are counted.
Table 3. Counting Arrangements for Line Code Violation Registers
Table 4. DS2155 Parameters
- INFO1.0
- Path Code Violation Count Registers in D4 framing mode with ERCNT.1 = 0
- Multiframes Out-of-Sync Count Registers in ESF mode with ERCNT.1 = 1
SR5.3 on transmit side
Note 1: Table 5 shows the the counting arrangements for the Line Code Violation Count Registers on the DS2155.
Note 2: Table 6 shows the detailed description of exactly what errors the PCVCR counts on the DS2155.
Note 3: Via the ERCNT.2 bit, the user has the choice in the D4 framing mode of counting errors in just the Ft bit pattern or in both the Ft and the Fs bit patterns.
Note 4: Table 7 contains the out-of-frame selection criteria.
Note 5: In the D4 framing mode, the SEFE bit (INFO1.2) only counts errors in the Ft pattern; in the ESF framing mode, only errors in the FPS pattern are counted.
Table 5. LCVCR Register in DS2155
Table 6. T1 Path Code Violation Counting Arrangements Using PCVCR Register in DS2155
Table 7. Out-of-Frame Criteria Selection in DS2155
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