Verilog头文件怎么包含

方法如下：陆明

Set the include.v file as global included and set its file_type to "Verilog Header".

If file_type is not set to Verilog Header, the include file will be treated as an ordinary Verilog file which can be referred by the other Verilog files and this causes the error above.

set_property file_type "Verilog Header" [get_files ../source_inclu/include.v]

set_property is_global_include true [get_files ../source_inclu/include.v]

Verilog可以从五个层次对电路（系统）进行描述，包括:系统级态腔、算法早闭告级、寄存器传输级（即RTL级）、门级、开关级。我们平时用的最多的为RTL级，故Verilog代码也经常被称为RTL代码。

就是配合测试用的数据或者侍圆是行为模型文件，一般来说verilog写的东西可以分成渗谈燃两类，一类是设计，就是具体的功能模块。另外一类是测试，就丛虚是testbench，激励文件属于这一类。他包含有接口的行为模型和配套的测试数据什么的。

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