VHDL语言编程，让led3灯以1HZ的频率闪烁，直接在我的上面修改即可

可以用外部中断计数，来实现流水灯的正转、暂停、以及反转和爆闪。。这是我前几天写的一个这样的程序，楼主可以结合protues 画图仿真，注意程序中所用到的IO端口就行了。

#include<reg52.h>

#include<intrins.h>

#define uchar unsigned char

uchar a,b

void delay(uchar z)

{

uchar i,j,k

for(i=zi>0i--)

for(k=20k>0k--)

for(j=110j>0j--)

}

void begain()

{

EA=1

EX0=1

IT0=1

}

void main()

{ a=b=0

P0=0xfe

begain()

while(1)

{

if(a==1)

{

P0=_crol_ (P0,1)

delay(50)

}

if(a==3)

{

P0=_cror_(P0,1)

delay(50)

}

if(a==4)

{

P0=0x00

delay(50)

P0=0xff

delay(50)

P0=0xfc

}

if(a==5)

{

a=1

}

}

}

void int0() interrupt 0

{

a++

if(a==5)

{

a=1

}

}

我用quartusⅡ已编译并且仿真都对的，我写的是0亮1灭，如果实际情况与这相反，你自己倒一下。

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_SIGNED.ALL

USE IEEE.numeric_std.all

ENTITY test IS

PORT (clock: in std_logic -----clock1加48MHz的信号

row: out std_logic_vector(0 to 7))

END test

ARCHITECTURE behave OF test IS

CONSTANT fp_clka:INTEGER:=12000000 ---扫描信号频率为2Hz

SIGNAL a: INTEGER RANGE 0 TO 12000001

signal saomiao :integer range 0 to 9

SIGNAL clka: std_logic

BEGIN

PROCESS (clock)

BEGIN

IF rising_edge(clock) THEN

IF a<fp_clka then --clka

a<=a+1

clka<=clka

ELSE

a<=0

clka<= NOT clka

end if

end if

end process

process(clka)

BEGIN

IF rising_edge(clka) THEN

saomiao<=saomiao+1

if saomiao=9 then

saomiao<=0

end if

case saomiao is---'1'代表不亮,'0'代表亮

when 0 =>row<="01111111"

when 1 =>row<="10111111"

when 2 =>row<="11011111"

when 3 =>row<="11101111"

when 4 =>row<="11110111"

when 5 =>row<="11111011"

when 6 =>row<="11111101"

when 7 =>row<="11111110"

when 8 =>row<="00000000"

when others =>row<="11111111"

END CASE

END IF

end process

END behave

定义按键，led灯，用switch语句

switch(keynum)

{

case 00000:begin led=5'b00000end

case 00001:begin led=5'b00001end

case 00010:begin led=5'b00010end

case 00100:begin led=5'b00100end

case 01000:begin led=5'b01000end

case 10000:begin led=5'b10000end

default:begin led=5'b0000end

}

思路应该是这样的

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