急！EDA程序设计改错问题，万分感谢!

好多地方都有问题。。。改正后如下：

LIBRARY ieee

USE ieee.STD_LOGIC_1164.ALL

use ieee.std_logic_unsigned.all

ENTITY abc IS

PORT (clk, rst : IN STD_LOGIC

load,EN : IN STD_LOGIC

din : IN STD_LOGIC_vector (7 downTO 0)

qb : out STD_LOGIC)

END abc

ARCHITECTURE one OF abc IS

signal reg : STD_LOGIC_vector(7 downTO 0)

begin

PROCESS(rst,load,EN,clk)

BEGIN

IF rst='1' THEN

reg <= "00000000"

ELSIF rising_edge(clk) THEN

IF load = '1' THEN

reg <= din

ELSIF EN='1' THEN

reg(6 downTO 0) <= reg(7 downTO 1)

END IF

END IF

END PROCESS

qb <= reg(1)

END one

程序改为： 01 LIBRARY IEEE 02 USE IEEE.STD_LOGIC_1164.ALL 03 USE IEEE.STD_LOGIC_UNSIGNED.ALL04 ENTITY LED7CNT IS 05 PORT (

15行的TMP=>"0000"因为你前面定义的是标准逻辑矢量STD_LOGIC_VECTOR(3 DOWNTO 0）

16行的else if 要改为elsif 若不改则要有两个end if 与if个数匹配，即再补个end if

我们一般都是把ELSE IF CLK'EVENT AND CLK = '1' THEN写为ELSIF CLK'EVENT AND CLK = '1' THEN则后面只有一个end if 就可以了。

一般我们编程时常把34WHEN OTHERS =>LED7S <= (OTHERS =>'0')

写成WHEN OTHERS =>NULL省的写那么多，但是不改也可以。你再试看看不行再问，我在我机子上运行可以

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY LED7CNT IS

PORT ( CLR : IN STD_LOGIC

CLK : IN STD_LOGIC

LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) )

END LED7CNT

ARCHITECTURE one OF LED7CNT IS

SIGNAL TMP : STD_LOGIC_VECTOR(3 DOWNTO 0)--integer range 16 downto 0

BEGIN

CNT:PROCESS(CLR,CLK)

BEGIN

IF CLR = '1' THEN

TMP <= "0000"

ELSIF CLK'EVENT AND CLK = '1' THEN

TMP <= TMP + 1

END IF

END PROCESS

OUTLED:PROCESS(TMP)

BEGIN

CASE TMP IS

WHEN "0000" => LED7S <= "0111111"

WHEN "0001" => LED7S <= "0000110"

WHEN "0010" => LED7S <= "1011011"

WHEN "0011" => LED7S <= "1001111"

WHEN "0100" => LED7S <= "1100110"

WHEN "0101" => LED7S <= "1101101"

WHEN "0110" => LED7S <= "1111101"

WHEN "0111" => LED7S <= "0000111"

WHEN "1000" => LED7S <= "1111111"

WHEN "1001" => LED7S <= "1101111"

WHEN OTHERS =>LED7S <= (OTHERS =>'0')

END CASE

END PROCESS

END one

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