实现DINA模型的matlab代码,还有失误率和猜测率参数估计

实现DINA模型的matlab代码,还有失误率和猜测率参数估计,第1张

%%%%%%%%%%%%%%%%把下面函数保存为gmcal.m文件%%%%%%%%%%% function gmcal=gm1(x) sizexd2 = size(x,2)%求数组长度 k=0for y1=x k=k+1if k>1 x1(k)=x1(k-1)+x(k)%累加生成 z1(k-1)=-0.5*(x1(k)+x1(k-1)) %z1维数减1,用于计算B yn1(k-1)=x(k)else x1(k)=x(k)end end %x1,z1,k,yn1 sizez1=size(z1,2)%size(yn1)z2 = z1'z3 = ones(1,sizez1)'YN = yn1'%转置 %YN B=[z2 z3]au0=inv(B'*B)*B'*YNau = au0'%B,au0,au afor = au(1)ufor = au(2)ua = au(2)./au(1)¯or,ufor,ua %输出预测的 a u 和 u/a的值 constant1 = x(1)-uaafor1 = -aforx1t1 = 'x1(t+1)'estr = 'exp'tstr = 't'leftbra = '('rightbra = ')'%constant1,afor1,x1t1,estr,tstr,leftbra,rightbra

这是我以前写的一个标准双端口ram,可以作为单端口或者双端口用

library ieee

use ieee.std_logic_1164.all

use IEEE.STD_LOGIC_ARITH.all

use IEEE.STD_LOGIC_UNSIGNED.all

entity blk_mem is

generic(

data_width : integer := 8 -- used to change the memory data's width

addr_width : integer := 11) -- used to change the memery address' width

port (

clka : in std_logic

dina : in std_logic_vector(data_width - 1 downto 0)

addra : in std_logic_vector(addr_width - 1 downto 0)

ena : in std_logic

wea : in std_logic

douta : out std_logic_vector(data_width - 1 downto 0)

clkb : in std_logic

dinb : in std_logic_vector(data_width - 1 downto 0)

addrb : in std_logic_vector(addr_width - 1 downto 0)

enb : in std_logic

web : in std_logic

doutb : out std_logic_vector(data_width - 1 downto 0))

end blk_mem

architecture blkmem of blk_mem is

type ram_template is array(2 ** addr_width - 1 downto 0) of std_logic_vector(data_width - 1 downto 0)

shared variable ram1 : ram_template

begin -- blkmem

process (clka)

begin -- process

if clka'event and clka = '1' then -- rising clock edge

if ena = '1' then

douta <= ram1(conv_integer(addra))

if wea = '1' then

ram1(conv_integer(addra)) := dina

end if

else

douta <= (others =>'0')

end if

end if

end process

process (clkb)

begin -- process

if clkb'event and clkb = '1' then -- rising clock edge

if enb = '1' then

doutb <= ram1(conv_integer(addrb))

if web = '1' then

ram1(conv_integer(addrb)) := dinb

end if

else

doutb <= (others =>'0')

end if

end if

end process

end blkmem


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