library ieee
use ieee.std_logic_1164.all
use IEEE.STD_LOGIC_ARITH.all
use IEEE.STD_LOGIC_UNSIGNED.all
entity blk_mem is
generic(
data_width : integer := 8 -- used to change the memory data's width
addr_width : integer := 11) -- used to change the memery address' width
port (
clka : in std_logic
dina : in std_logic_vector(data_width - 1 downto 0)
addra : in std_logic_vector(addr_width - 1 downto 0)
ena : in std_logic
wea : in std_logic
douta : out std_logic_vector(data_width - 1 downto 0)
clkb : in std_logic
dinb : in std_logic_vector(data_width - 1 downto 0)
addrb : in std_logic_vector(addr_width - 1 downto 0)
enb : in std_logic
web : in std_logic
doutb : out std_logic_vector(data_width - 1 downto 0))
end blk_mem
architecture blkmem of blk_mem is
type ram_template is array(2 ** addr_width - 1 downto 0) of std_logic_vector(data_width - 1 downto 0)
shared variable ram1 : ram_template
begin -- blkmem
process (clka)
begin -- process
if clka'event and clka = '1' then -- rising clock edge
if ena = '1' then
douta <= ram1(conv_integer(addra))
if wea = '1' then
ram1(conv_integer(addra)) := dina
end if
else
douta <= (others =>'0')
end if
end if
end process
process (clkb)
begin -- process
if clkb'event and clkb = '1' then -- rising clock edge
if enb = '1' then
doutb <= ram1(conv_integer(addrb))
if web = '1' then
ram1(conv_integer(addrb)) := dinb
end if
else
doutb <= (others =>'0')
end if
end if
end process
end blkmem
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