分频
，算好闪烁的时间
2.搞一个计数器，然后case语句，
light随着计数器变化
也可以考虑移位 *** 作~~~多看看书就会
我给你写了一个代码，没有仿真，里面有简单注释，要是调试出了什么问题或者看不懂可以继续追问，如果没问题请采纳！module LED
(
input clk_33,
input reset_n,
input switch,
output led_red,
output led_yellow,
output led_bule
)
// 假设PWM的频率为1k：T = 1/1k = 1ms
// 这个频率可以根据你自己的需要设定然后修改num和t的值即可，不过要注意将相关寄存器的位数做对应修改
// 将1ms再分为256个份，每一份：t = T/256 = 3.9us；
// 以33MHz时钟产生3.9us的定时：N = 3.9*10E(-6)/(1/33000000) = 128.7，取129；
// ==============================
parameter t = 8'd128
parameter num = 8'd255
// ==============================
reg [1:0] i//0:等待用户按键；1:等待完成信号，切换至状态0；
reg iscount//开始计数信号
reg isdone//完成信号
// --- --- ---
always @ ( posedge clk_33 or negedge reset_n )
if( !reset_n )
begin
i <= 1'b0
iscount <= 1'b0
end
else
case( i )
2'd0:
if( switch )
begin
i <= i + 1'b1
iscount <= 1'b1
end
else
begin
i <= i
iscount <= iscount
end
2'd1:
if( isdone )
begin
i <= 2'd0
iscount <= 1'b0
end
else
begin
i <= i
iscount <= iscount
end
endcase
// ==============================
reg [7:0] count1//产生3.9us
// --- --- ---
always @ ( posedge clk_33 or negedge reset_n )
if( !reset_n )
count1 <= 8'd0
else if( iscount )
count1 <= count1 + 1'b1
else if( count1 == t )
count1 <= 8'd0
else
count1 <= 8'd0
// ==============================
reg [7:0] count2//产生1ms
reg [8:0] length//控制PWM中高电平的时间
reg [1:0] step//0:等待开始信号；1:渐亮；2:渐暗；3:切换至状态0等待开始信号
// --- --- ---
always @ ( posedge clk_33 or negedge reset_n )
if( !reset_n )
begin
count2 <= 8'd0
length <= 9'd1
step <= 2'd0
isdone <= 1'b0
end
else
case( step )
2'd0:
if( iscount )
step <= step + 1'b1
else
step <= step
2'd1:
if( count2 == 8'd255 )
begin
if( length == 8'd255 )
begin
length <= length - 1'b1
count2 <= 8'd0
step <= step + 1'b1
end
else
begin
length <= length + 1'b1
count2 <= 8'd0
end
end
else if( count1 == t )
count2 <= count2 + 1'b1
else
2'd2:
if( count2 == 8'd255 )
begin
if( length == 8'd0)
begin
step <= step + 1'b1
count2 <= 8'd0
isdone <= 1'b1
end
else
begin
length <= length - 1'b1
count2 <= 8'd0
end
end
else if( count1 == t )
count2 <= count2 + 1'b1
else
2'd3:
begin
isdone <= 1'b0
step <= 2'd0
end
endcase
// ==============================
assign led_red = ( length >count2 ) ? 1'b1 : 1'b0
assign led_yellow = ( length >count2 ) ? 1'b1 : 1'b0
assign led_bule = ( length >count2 ) ? 1'b1 : 1'b0
// ==============================
endmodule
/*LCD12864显示程序此程序控制LCD12864液晶屏,IC为KS0108或兼容型号
图形文件获取方法:
在字模提取V21软件中 ,导入一幅128*64黑白图像.
* 参数设置：
* 参数设置->其它选项，选择纵向取模，勾上字节倒序，保留逗号,
* 取模方式为C51。
将生成的数组通过keilc等C编译软件,在编译软件中新建一工程,写入源程序如下:
unsigned char code tab[]=
{
//图像数据
}
编译此工程将得到hex文件.在QII中使用lpm_rom宏功能模块中调用此hex文件.
*
*******************************************************************************/
module newlcd(clock,rst_n,rs,rw,en,data,lcd_cs)
// I/O口声明
input clock //系统时钟
input rst_n //复位信号
output[1:0] lcd_cs //
outputrs //1：数据模式；0：指令模式
outputrw //1：读 *** 作；0：写 *** 作
outputen //使能信号，写 *** 作时在下降沿将数据送出；读 *** 作时保持高电平
output[7:0] data//LCD数据总线
// I/O寄存器
reg rs
reg en
reg[1:0] lcd_cs
reg[7:0] data
//内部寄存器
reg[3:0] state //状态机
reg[3:0] next_state
reg[20:0] div_cnt //分频计数器
reg[9:0] cnt //写 *** 作计数器
reg cnt_rst //写 *** 作计数器复位信号
wire[7:0] showdata //要显示的数据
reg[1:0] cs_r
reg [2:0] page_addr
reg [5:0] row_addr
//内部网线
wire clk_div//分频时钟
wire clk_divs
wire page_done //写一行数据完成标志位
wire frame_done //写一屏数据完成标志位
wire left_done
//状态机参数
parameter idle =4'b0000,
setbase_1=4'b0001,
setbase_2=4'b0011,
setmode_1=4'b0010,
setmode_2=4'b0110,
SETpage_addr_1=4'b0111,
SETpage_addr_2=4'b0101,
SETrow_addr_1 =4'b1101,
SETrow_addr_2 =4'b1111,
write_right_1 =4'b1110,
write_right_2 =4'b1010,
write_nextpage_1 =4'b1011,
write_nextpage_2 =4'b1001,
wr_data_1 =4'b0100,
wr_data_2 =4'b1100
// set_1=4'b1000
//******************************代码开始*********************************
assign rw = 1'b0 //对LCD始终为写 *** 作
//时钟分频
always@(posedge clock or negedge rst_n)
begin
if(!rst_n)
div_cnt <= 0
else
div_cnt <= div_cnt+1'b1
end
assign clk_div = (div_cnt[15:0] == 20'h7fff)
//状态机转向
always@(posedge clock or negedge rst_n)
begin
if(! rst_n)
state <= idle
else if(clk_div)
state <= next_state
end
//************************状态机逻辑*********************************
always@(state or page_done or left_done or frame_done or cnt or showdata or page_addr or row_addr or cs_r)
begin
rs <= 1'b0
en <= 1'b0
lcd_cs <= cs_r
cnt_rst <= 1'b0
data <= 8'h0
case(state)
idle:
begin
next_state <= setbase_1
cnt_rst <= 1'b1
end
//**************************初始化LCD********************************
setbase_1: //基本指令 *** 作
begin
lcd_cs <= 2'b11
next_state <= setbase_2
data <= 8'hc0
en <= 1'b1
end
setbase_2:
begin
lcd_cs <= 2'b11
next_state <= setmode_1
data <= 8'hc0
end
//******************************************************************
setmode_1:
begin
lcd_cs <= 2'b11
next_state <= setmode_2
data <= 8'h3f
en <=1'b1
end
setmode_2:
begin
next_state <= SETpage_addr_1
data <= 8'h3f
end
//******************************************************************
SETpage_addr_1: //设置页地址
begin
next_state <= SETpage_addr_2
data <=
en <= 1'b1
end
SETpage_addr_2:
begin
next_state <= SETrow_addr_1
data <=
end
SETrow_addr_1: //设置列地址
begin
next_state <= SETrow_addr_2
data <=
en <= 1'b1
end
SETrow_addr_2:
begin
next_state <= wr_data_1
data <=
end
//******************************************************************
/*
write_right_1: //写完左半屏64个,换为右半屏显示
begin
next_state <=write_right_2
row_addr <= 0
end
write_right_2:
begin
next_state <= SETpage_addr_1
end
//******************************************************************
write_nextpage_1: //写完全一行128个
begin
next_state <=write_nextpage_2
row_addr <= 0
end
write_nextpage_2:
begin
next_state <= SETpage_addr_1
end
*/
//******************************************************************
wr_data_1: //写数据到图形显示区
begin
next_state <= wr_data_2
rs <= 1'b1
en <= 1'b1
data <= showdata
end
wr_data_2:
begin
rs <= 1'b1
data <= showdata
if(left_done) //写完左半屏数据64个
begin
if(page_done) //写完一页数据128个
begin
if(frame_done) //写完一屏数据（8页）
next_state <= idle
else
// next_state <= write_nextpage_1
next_state <= SETpage_addr_1
end
else
// next_state <= write_right_1
next_state <= SETpage_addr_1
end
else
next_state <= wr_data_1
end
default: next_state <= idle
endcase
end
//********************************************************************
always@(posedge clock)
begin
if(clk_div)
begin
if(cnt_rst)
begin
cnt <= 0
end
else if(state == wr_data_2)
begin
cnt <= cnt+1'b1
end
end
end
//****************************************************
always@(posedge clock or negedge rst_n)
if(!rst_n)
begin
cs_r <= 2'b01
page_addr <= 0
end
else
if(clk_div &&(state == wr_data_2))
if(page_done)//
begin
cs_r <= 2'b01
page_addr <= page_addr + 1'b1//一页写完时写下一页
end
else
if(left_done)
begin
cs_r <= 2'b10
end
//*********************************************************************
//********************************************************************
assign left_done = (cnt[5:0] == 6'd63) //写完左半屏数据64个
assign page_done = (cnt[6:0] == 7'd127) //写完一页数据128个
assign frame_done = (cnt[9:4] == 7'h3f) //写完一屏数据
//***********************************************************************
//*******************************************************************
//调用ROM（图片数据）
rom rom(.address(cnt+'d8),.clock(clock),.q(showdata))
endmodule
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