编写上升沿触发的D触发器的VHDL语言程序

你说的置位就是有一个set输入(q=1)，清零应该可以用复位键reset吧(q=0)。

library

ieee

use

ieee.std_logic_1164.all

entity

sync_rsdff

is

port(d,clk

:

in

std_logic

set

:

in

std_logic

reset:

in

std_logic

q,qb

:

out

std_logic)

end

sync_rsdff

architecture

rtl_arc

of

sync_rsdff

is

process(clk)

begin

if

(clk'event

and

clk='1')

then

if(set='0'

and

reset='1')

then

q<='1'

qb<='0'

elsif

(set='1'

and

reset='0')

then

q<='0'

qb<='1'

else

q<=d

qb<=not

d

end

if

end

process

end

rtl_arc

以上是同步置位/复位的d触发器。

我也在忙我自己的论文啊。

核心就是reset是用clk来同步，即只能在clk的沿到来时reset。

library ieee

use ieee.std_logic_1164.all

use ieee.numeric_std.all

use ieee.std_logic_unsigned.all

entity dff_sr is

port(

clk: in std_logic

rst_n: in std_logic

din: in std_logic

qout: out std_logic)

end dff_sr

architecture str of dff_sr is

begin

process(clk,rst_n)

begin

if clk'event and clk = '1' then

if rst_n = '1' then

qout <= '0'

else

qout <= din

end if

end if

end process

end str

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