如何用VHDL实现分频？

模N计数器的实现

一般设计中用到计数器时，我们可以调用lpm库中的计数器模块，也可以采用VHDL语言自己设计一个模N计数器。本设计采用VHDL语言设计一个最大模值为16的计数器。输入端口为：使能信号en，复位信号clr和时钟信号clk输出端口为：qa、qb、qc、qd。其VHDL语言描述略。

带使能控制的异或门的实现

输入端为：xor_en：异或使能，a和b：异或输入输出端为：c：异或输出。当xor_en为高电平时，c输出a和b的异或值。当xor_en为低电平时，c输出信号b。其VHDL语言略。

2分频(触发器)的实现

输入端为：时钟信号clk，输入信号d输出端为：q：输出信号a，q1：输出信号a反。其VHDL语言略。

4.分频器的实现

本设计采用层次化的设计方法，首先设计实现分频器电路中各组成电路元件，然后通过元件例化的方法，调用各元件，实现整个分频器。其VHDL语言略。

这个简单啊，你把这个文件封装成元件，用原理图来做，你用你自己的十分频的代码封装成一个十分频的元件，用原理图来做，使用你封装的十分频元件，把其输出做为下一个十分频元件的输入，你要做10^n分频，你就串接n个十分频的元件即可！不过所有的十分频元件的时钟是共用一个时钟！

分频没必要一定用锁相环啊，普通分频就可以了啊，锁相环一般是用倍频的，我把代码给你，你研究一下，这个电路我前两天刚调试成功

-----------------------------------------------------------------------

-- This section contains clock manager.

-----------------------------------------------------------------------

IBUFG_clock : IBUFG

generic map (

IBUF_DELAY_VALUE =>"0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only)

IOSTANDARD =>"DEFAULT")

port map (

O =>clkin_buf, -- Clock buffer output

I =>clk_in -- Clock buffer input (connect directly to top-level port)

)

BUFG_clk_sys : BUFG

port map (

O =>clk_sys, -- Clock buffer output

I =>CLK0 -- Clock buffer input

)

BUFG_clk_fx : BUFG

port map (

O =>TX_CLK, -- Clock buffer output

I =>CLKFX -- Clock buffer input

)

DCM_gnet : DCM

generic map (

CLKDV_DIVIDE =>8.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5

-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0

CLKFX_DIVIDE =>1, -- Can be any interger from 1 to 32

CLKFX_MULTIPLY =>4, -- Can be any integer from 1 to 32

CLKIN_DIVIDE_BY_2 =>FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature

CLKIN_PERIOD =>0.0, -- Specify period of input clock

CLKOUT_PHASE_SHIFT =>"NONE", -- Specify phase shift of NONE, FIXED or VARIABLE

CLK_FEEDBACK =>"1X", -- Specify clock feedback of NONE, 1X or 2X

DESKEW_ADJUST =>"SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or

-- an integer from 0 to 15

DFS_FREQUENCY_MODE =>"LOW", -- HIGH or LOW frequency mode for frequency synthesis

DLL_FREQUENCY_MODE =>"LOW", -- HIGH or LOW frequency mode for DLL

DUTY_CYCLE_CORRECTION =>TRUE, -- Duty cycle correction, TRUE or FALSE

FACTORY_JF =>X"C080", -- FACTORY JF Values

PHASE_SHIFT =>0,-- Amount of fixed phase shift from -255 to 255

STARTUP_WAIT =>FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE

port map (

CLK0 =>CLK0, -- 0 degree DCM CLK ouptput

-- CLK180 =>CLK180, -- 180 degree DCM CLK output

-- CLK270 =>CLK270, -- 270 degree DCM CLK output

CLK2X =>CLK2X, -- 2X DCM CLK output --100MHZ

-- CLK2X180 =>CLK2X180, -- 2X, 180 degree DCM CLK out

-- CLK90 =>CLK90, -- 90 degree DCM CLK output

-- CLKDV =>CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)

CLKFX =>CLKFX, -- DCM CLK synthesis out (M/D)

-- CLKFX180 =>CLKFX180, -- 180 degree CLK synthesis out

-- LOCKED =>LOCKED, -- DCM LOCK status output

-- PSDONE =>PSDONE, -- Dynamic phase adjust done output

-- STATUS =>STATUS, -- 8-bit DCM status bits output

CLKFB =>clk_sys, -- DCM clock feedback

CLKIN =>clkin_buf, -- Clock input (from IBUFG, BUFG or DCM)

-- PSCLK =>PSCLK, -- Dynamic phase adjust clock input

-- PSEN =>'0', -- Dynamic phase adjust enable input

-- PSINCDEC =>PSINCDEC, -- Dynamic phase adjust increment/decrement

RST =>rst_manu_h-- DCM asynchronous reset input

)

库文件

library IEEE

Library UNISIM

use IEEE.STD_LOGIC_1164.ALL

use IEEE.STD_LOGIC_UNSIGNED.ALL

use IEEE.STD_LOGIC_ARITH.ALL

use UNISIM.vcomponents.all

---