reg [15:0] count = 0
// 在每一个时钟周期内更新计时器的值
always @(posedge clk) begin
count <= count + 1
end
always @(posedge clk) begin
if (count == 16'hffff) begin
// 更新流水灯的状态
// ...
// 重置计时器的值
count <= 0
end
end
module run_led(clk,rst,led)//module portinput clk//system clock
input rst//system reset
output [7:0] led// 8bits led
reg [7:0] led
reg [25:0] count
always @ (posedge clk ) begin
if(rst || count[25]==1) begin
count<=26'b0
end
else
count<=count+1
end
always @ (posedge clk) begin
if(rst)
led<=8'b0000_0001
else begin
if(count[25]==1) begin
led<=((led<<1)+1)
end
end
end
endmodule
这是我自己写的,实验正确符合楼主要求!嘿嘿。。。
欢迎分享,转载请注明来源:内存溢出
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