怎么写verilog 测试程序

给你写一个例子，下面是一个设计文件和一个对应的测试程序，希望能起到抛砖引玉的和用：

/*

File Name : test.v

Author: www.flxc.net

Data : 2010-10-14 20:20:52

Description : This module is to shift the 32 bit input data with clock edges.

*/

`timescale 1ns/1ns

`define period 10

module test(

clk,

rst_n,

data_i,

data_o

)

input clk

input rst_n

input [31:0] data_i

output [31:0] data_o

reg [31:0] data_o

always@(posedge clk or negedge rst_n)

beg

if(!rst_n)

data_o <= 32'b0

else

data_o <= data_i >>1

end

endmodule

module test_tb

reg clk

reg rst_n

reg [31:0] data_i

wire [31:0] data_o

initial

begin

clk=1'b1

rst_n=1'b1

data_i=32'b1010_1111_1000_1111_1111_0000_0001_0000

#(`period/3)

rst_n=1'b0

#(`period/3)

rst_n=1'b1

#100000000

$stop

end

always #(`period/2) clk=~clk

endmodule

下面的代码我已经用modelsim仿真过了，没有问题。

module count(out,clk,rst)//源程序

input clk,rst

output[3:0] out

reg[3:0] out

initial out=4'd0

always @(posedge clk or negedge rst)

begin

if(!rst) out=4'd0

else

begin

out=out+4'd1

if(out==4'd1||out==4'd6||out==4'd8) out=out+4'd1

if(out==4'd5) out=out+4'd2

end

end

endmodule

`timescale 1ns/1ns //测试程序

`include "count.v"

module count_tp

reg clk,rst

wire[3:0] out

parameter DELY=100

count mycount(out,clk,rst)

always #(DELY/2) clk=~clk

initial

begin

clk=0rst=1

#(DELY*5) rst=0

#DELY rst=1

#(DELY*20) $finish

end

initial $monitor($time,,,"clk=%d rst=%d out=%d",clk,rst,out)

endmodule

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