密码锁的设计用VHDL语言描述

一、系统功能概述

数字密码锁实现：1、了不需要带钥匙，只要记住开锁密码即可开锁的功能。2、在输入密码正确后，还可以修改密码。3、在输入密码的过程中，不显示密码，只显示无规律的提示某位密码是否输入完毕，防止了密码的泄漏，大大加强了密码锁的保密性。

本演示系统实现了：1、输入密码正确后，正确小灯（led）亮，错误小灯（led1）不亮；2、正确修改密码后，正确小灯（led）不亮，错误小灯雹扰（led1）不亮；3、输入错误密码，正确小灯（led）不亮，错误小灯（led1）亮，并有1KHz闹铃声产生；4、按下reset后，密码归为初始密码。

开锁代码为8位二进制源态旦数，当输入代码的位数和位值与锁内给定的密码一致，且按规定程序开锁时，方可开锁，并点亮开锁指示灯D3。否则系统进入“错误”状态，并发出报警信号。

开锁程序由设计者确定，并锁内给定的密码是可调的，且预置方便，保密性好。

串行数字锁的报警方式是点亮指示灯D6，并使喇叭鸣叫来报警，报警动作直到按下复位开关，闭乱报警才停止。此时，数字锁自动进入等待下一次开锁的状态。

源代码

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_unsigned.all

entity code is

port( clk: in std_logic--电路工作时的时钟信号

clk1: in std_logic--闹铃产生需要的时钟信号

k: in std_logic--高电平表示输入1

led: out std_logic--输入正确时亮

led1: out std_logic--输入错误时亮

reset: in std_logic-- 按下时复位

want: in std_logic--是否修改密码

alarm: out std_logic--输出闹铃声

show: out std_logic_vector(3 downto 0))--提示作用

end

architecture a of code is

signal temp: std_logic_vector(3 downto 0)--输入一位加1

signal code: std_logic_vector(7 downto 0)--储存密码

signal getcode: std_logic_vector(7 downto 0)--储存修改后的密码

signal counter: std_logic_vector(3 downto 0)--计数

signal allow: std_logic--是否允许修改密码

signal ring:std_logic--是否接通闹铃

begin

process(clk)

begin

if ring='1' then

alarm<=clk1--闹铃接通

else

alarm<='0'--闹铃截至

end if

if reset='1' then--按下reset后，密码归为初始密码

getcode<="00000000"--初始密码

counter<="0000"--内部计数

code<="11001000"--密码

led<='0'

led1<='0'

allow<='0'

elsif clk'event and clk='1' then--输入clk脉冲，则接收1位密码

getcode<=getcode(6 downto 0)&k--将这1位密码并入getcode中的最后一位

if counter="1000" then--输入为8位数码时比较

if code=getcode then

led<='1'--正确灯亮

led1<='0'

ring<='0'

allow<='1'--允许修改密码

elsif allow='1' and want='1' then--如果允许输入且想输入

code<=getcode--输入新密码

led<='0'

led1<='0'

else

allow<='0'

led<='0'

led1<='1'--错误灯亮

ring<='1'--闹铃响

end if

counter<="0000"--重新计数

else

counter<=counter+1--累加

temp<=temp+1--为防止泄露密码，特别设置

end if

end if

show <= temp

end process

end

完整程序如下：其中：clk0_divide_by =>2,为分频因子

clk0_duty_cycle =>50,为占空丛森比

clk0_multiply_by =>3,为倍频因子，这些数据都可以根据需要自行设定

还有疑问裤搭的可以问我

LIBRARY ieee

USE ieee.std_logic_1164.all

LIBRARY altera_mf

USE altera_mf.all

ENTITY pll0 IS

PORT

(

inclk0 : IN STD_LOGIC := '渗纯亩0'

c0 : OUT STD_LOGIC

)

END pll0

ARCHITECTURE SYN OF pll0 IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0)

SIGNAL sub_wire1 : STD_LOGIC

SIGNAL sub_wire2 : STD_LOGIC

SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0)

SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0)

SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0)

COMPONENT altpll

GENERIC (

clk0_divide_by : NATURAL

clk0_duty_cycle : NATURAL

clk0_multiply_by : NATURAL

clk0_phase_shift : STRING

compensate_clock : STRING

inclk0_input_frequency : NATURAL

intended_device_family : STRING

lpm_hint : STRING

lpm_type : STRING

operation_mode : STRING

port_activeclock : STRING

port_areset : STRING

port_clkbad0 : STRING

port_clkbad1 : STRING

port_clkloss : STRING

port_clkswitch : STRING

port_configupdate : STRING

port_fbin : STRING

port_inclk0 : STRING

port_inclk1 : STRING

port_locked : STRING

port_pfdena : STRING

port_phasecounterselect : STRING

port_phasedone : STRING

port_phasestep : STRING

port_phaseupdown : STRING

port_pllena : STRING

port_scanaclr : STRING

port_scanclk : STRING

port_scanclkena : STRING

port_scandata : STRING

port_scandataout : STRING

port_scandone : STRING

port_scanread : STRING

port_scanwrite : STRING

port_clk0 : STRING

port_clk1 : STRING

port_clk2 : STRING

port_clk3 : STRING

port_clk4 : STRING

port_clk5 : STRING

port_clkena0 : STRING

port_clkena1 : STRING

port_clkena2 : STRING

port_clkena3 : STRING

port_clkena4 : STRING

port_clkena5 : STRING

port_extclk0 : STRING

port_extclk1 : STRING

port_extclk2 : STRING

port_extclk3 : STRING

)

PORT (

clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)

inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)

)

END COMPONENT

BEGIN

sub_wire4_bv(0 DOWNTO 0) <= "0"

sub_wire4<= To_stdlogicvector(sub_wire4_bv)

sub_wire1<= sub_wire0(0)

c0<= sub_wire1

sub_wire2<= inclk0

sub_wire3<= sub_wire4(0 DOWNTO 0) &sub_wire2

altpll_component : altpll

GENERIC MAP (

clk0_divide_by =>2,

clk0_duty_cycle =>50,

clk0_multiply_by =>3,

clk0_phase_shift =>"0",

compensate_clock =>"CLK0",

inclk0_input_frequency =>10000,

intended_device_family =>"Cyclone II",

lpm_hint =>"CBX_MODULE_PREFIX=pll1",

lpm_type =>"altpll",

operation_mode =>"NORMAL",

port_activeclock =>"PORT_UNUSED",

port_areset =>"PORT_UNUSED",

port_clkbad0 =>"PORT_UNUSED",

port_clkbad1 =>"PORT_UNUSED",

port_clkloss =>"PORT_UNUSED",

port_clkswitch =>"PORT_UNUSED",

port_configupdate =>"PORT_UNUSED",

port_fbin =>"PORT_UNUSED",

port_inclk0 =>"PORT_USED",

port_inclk1 =>"PORT_UNUSED",

port_locked =>"PORT_UNUSED",

port_pfdena =>"PORT_UNUSED",

port_phasecounterselect =>"PORT_UNUSED",

port_phasedone =>"PORT_UNUSED",

port_phasestep =>"PORT_UNUSED",

port_phaseupdown =>"PORT_UNUSED",

port_pllena =>"PORT_UNUSED",

port_scanaclr =>"PORT_UNUSED",

port_scanclk =>"PORT_UNUSED",

port_scanclkena =>"PORT_UNUSED",

port_scandata =>"PORT_UNUSED",

port_scandataout =>"PORT_UNUSED",

port_scandone =>"PORT_UNUSED",

port_scanread =>"PORT_UNUSED",

port_scanwrite =>"PORT_UNUSED",

port_clk0 =>"PORT_USED",

port_clk1 =>"PORT_UNUSED",

port_clk2 =>"PORT_UNUSED",

port_clk3 =>"PORT_UNUSED",

port_clk4 =>"PORT_UNUSED",

port_clk5 =>"PORT_UNUSED",

port_clkena0 =>"PORT_UNUSED",

port_clkena1 =>"PORT_UNUSED",

port_clkena2 =>"PORT_UNUSED",

port_clkena3 =>"PORT_UNUSED",

port_clkena4 =>"PORT_UNUSED",

port_clkena5 =>"PORT_UNUSED",

port_extclk0 =>"PORT_UNUSED",

port_extclk1 =>"PORT_UNUSED",

port_extclk2 =>"PORT_UNUSED",

port_extclk3 =>"PORT_UNUSED"

)

PORT MAP (

inclk =>sub_wire3,

clk =>sub_wire0

)

END SYN

你还是没有描述，我只好简单写了洞灶下，先描述一下该密码锁原理：

1。密纳大扮码锁有4位0bit,1bit,2bit,3bit，每位接收‘0’ 和‘1’ 两种输入。

2。每次输入密码，需按照0->1->2->3bit 的顺序输入，否则无法开锁。

3。如果按下0bit输入后一段时间内不开锁，则锁会锁定，无法开锁。再过一会，方能再次重新开。

4。如果一旦有按键按错，则锁会锁住，一段时间无法开锁。过一段时间需从0bit重新依次输入。

5。0,1,2,3依次密码正确，则开锁

程序如下（编译过了，还没来得及仿真，你可以自己做做，有错误正好可以学习着修改，呵呵）：

LIBRARY ieee

USE ieee.std_logic_1164.all

USE ieee.std_logic_unsigned.all

entity digitalkey is

port (

clk : in std_logic

rst : in std_logic

key0 : in std_logic

key1 : in std_logic

key2 : in std_logic

key3 : in std_logic

keyopen : out std_logic)

end entity

architecture str of digitalkey is

signal timer1_cnt : std_logic_vector(4 downto 0)

signal timer2_cnt : std_logic_vector(2 downto 0)

signal key_err: std_logic

signal key_lock1 : std_logic

signal key_lock2 : std_logic

signal key_open : std_logic

type key_type is (idle, key0_ok, key1_ok,key2_ok,key3_ok)

signal key_fsm : key_type

constant key : std_logic_vector(3 downto 0) :=("0101")

begin

process(rst,clk)

begin

if rst = '1' then

key_fsm <= idle

key_err <= '0'

key_open <= '0'

elsif clk'event and clk = '仿余1' then

if key_lock1='0' and key_lock2='0' then

case key_fsm is

when idle =>

key_err <= '0'

if key0 = key(0) then

key_fsm <= key0_ok

else

key_fsm <= idle

key_err <= '1'

end if

when key0_ok =>

if key1 = key(1) then

key_fsm <= key1_ok

else

key_fsm <= idle

key_err <= '1'

end if

when key1_ok =>

if key2 = key(2) then

key_fsm <= key2_ok

else

key_fsm <= idle

key_err <= '1'

end if

when key2_ok =>

if key3 = key(3) then

key_fsm <= idle

key_open <= '1'

else

key_fsm <= idle

key_err <= '1'

end if

when others =>

key_fsm <= idle

key_err <= '1'

end case

end if

end if

end process

process(rst,clk)

begin

if rst = '1' then

timer1_cnt <= (others =>'0')

key_lock1 <= '0'

elsif clk'event and clk = '1' then

if key0 = '1' then

if timer1_cnt = 15 then

key_lock1 <= '1'

elsif timer1_cnt = 30 then

timer1_cnt <= (others =>'0')

key_lock1 <= '0'

else

timer1_cnt <= timer1_cnt + 1

key_lock1 <= '0'

end if

else

key_lock1 <= '1'

end if

else

key_open <= '0'

end if

end process

process(rst,clk)

begin

if rst = '1' then

timer2_cnt <= (others =>'0')

key_lock2 <= '0'

elsif clk'event and clk = '1' then

if timer2_cnt = 7 then

timer2_cnt <= (others =>'0')

key_lock2 <= '0'

elsif key_err = '1' then

timer2_cnt <= timer2_cnt + 1

key_lock2 <= '1'

end if

end if

end process

keyopen <= key_open

end str

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