求Verilog HDL程序

1

module sig2component(clk, rst_n, din, dout)

inputclk

inputrst_n

input [7:0]din

output [7:0] dout

always @ (posedge clk or negedge rst_n)

if (!rst_n)

dout <= 0

else if (din[7]) begin

dout[6:0] <= ~din[6:0] + 7'游猜d1

dout[7] <= din[7]

end

else

dout <神型型= din

endmodule

2

module compare(clk, rst_n, din, flag_out)

input clk, rst_n

input [3:0]din

output flag_out

always @ (posedge clk or negedge rst_n)

if (!rst_n)

flag_out <= 0

else if (din >租念 4'd4)

flag_out <= 1'b1

else

flag_out <= 1'b0

input [7:0] aoutput [7:0] bint ireg [7:0] calways @(a) begin for (i=0i<旦桐陵8i++) c[i] = !a[i]endalways @(c) begin b[7:0] = c[7:0] + 8'模戚轮如d1end

module CNT10 (CLK, RST, EN, CQ, COUT)

input CLK,RST,EN

output[3:0] CQ

output COUT

reg[3:0] CQ,CQI

reg COUT

always @(posedge CLK)//好锋检测时钟上升沿

begin : u1

if (RST == 1'b1)//计数器复位友颂晌

begin

CQI={4{1'b0}}

end

begin

if(EN==1'b1)//检测是否允许计数

begin

if (CQI<9)

begin

CQI=CQI+1//允许计数

end

else

begin

CQI={4{1'b0}}//大于9，计数值清零

end

end

end

if (CQI==9)

begin

COUT<=1'b1 //计数大于9，输出进位信号

end

else

begin

COUT<=1'b0

end

CQ<=CQI //将计数值樱兄向端口输出

end

endmodule

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