verilog写成vhdl时出现的问题 100分求助

IF clk'EVENT AND clk = '1' THEN

d0<= '0'

d1<= '0'

d2<正正锋= '0'

这几句已经注定将d[2:0]在每个时钟节拍都被置0了举晌. 建议在定义d[2:0]或复位清塌时设它的初值.譬如:

always @(posedge clk or negedge rst_n)

if (!rst_n) begin

d[2:0] <=0

else

...

闲着没事，我来帮你转逗坦吧

LIBRARY ieee

USE ieee.std_logic_1164.all

USE ieee.std_logic_unsigned.all

ENTITY key_led is

port(

key_in : in std_logic_vector(7 downto 0)

led: out std_logic_vector(7 downto 0))

end ENTITY

ARCHITECTURE str of key_led is

begin

process(key_in)

begin

case key_in is

when "11111110" =>

led = "00000001"

when "11111101" =>

led = "00000010"

......中间自己照抄吧

when others

led = "00000000"

end case

end process

end str

不过话说你这个verilog的程序腊指亏也不咋地啊，clk都没有还要定义两个reg，综合的时候肯定被干掉了，没有触发器的轮神

LIBRARY ieee

USE ieee.std_logic_1164.all

USE ieee.std_logic_unsigned.all

ENTITY my_uart_rx IS

PORT (

clk: IN STD_LOGIC

rst_n : IN STD_LOGIC

rs232_rx : IN STD_LOGIC

rx_data: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

rx_int : OUT STD_LOGIC

clk_bps: IN STD_LOGIC

bps_start : OUT STD_LOGIC

)

END my_uart_rx

ARCHITECTURE trans OF my_uart_rx IS

SIGNAL rs232_rx0: STD_LOGIC

SIGNAL rs232_rx1: STD_LOGIC

SIGNAL rs232_rx2: STD_LOGIC

SIGNAL rs232_rx3: STD_LOGIC

SIGNAL neg_rs232_rx : STD_LOGIC

SIGNAL bps_start_r : STD_LOGIC

SIGNAL num : STD_LOGIC_VECTOR(3 DOWNTO 0)

SIGNAL rx_data_r: STD_LOGIC_VECTOR(7 DOWNTO 0)

SIGNAL rx_temp_data : STD_LOGIC_VECTOR(7 DOWNTO 0)

-- Declare intermediate signals for referenced outputs

SIGNAL rx_int_xhdl0 : STD_LOGIC

BEGIN

-- Drive referenced outputs

rx_int <= rx_int_xhdl0

PROCESS (clk, rst_n)

BEGIN

IF ((NOT(rst_n)) = '1') THEN

rs232_rx0 <= '0'

rs232_rx1 <= '汪正0'

rs232_rx2 <= '0'

rs232_rx3 <= '0'

ELSIF (clk'明陵银EVENT AND clk = '1') THEN

rs232_rx0 <= rs232_rx

rs232_rx1 <= rs232_rx0

rs232_rx2 <= rs232_rx1

rs232_rx3 <= rs232_rx2

END IF

END PROCESS

neg_rs232_rx <= rs232_rx3 AND rs232_rx2 AND NOT(rs232_rx1) AND NOT(rs232_rx0)

PROCESS (clk, rst_n)

BEGIN

IF ((NOT(rst_n)) = '1') THEN

bps_start_r <= 'Z'

rx_int_xhdl0 <= '0'激宴

ELSIF (clk'EVENT AND clk = '1') THEN

IF (neg_rs232_rx = '1') THEN

bps_start_r <= '1'

rx_int_xhdl0 <= '1'

ELSIF (num = "1100") THEN

bps_start_r <= '0'

rx_int_xhdl0 <= '0'

END IF

END IF

END PROCESS

bps_start <= bps_start_r

PROCESS (clk, rst_n)

BEGIN

IF ((NOT(rst_n)) = '1') THEN

rx_temp_data <= "00000000"

num <= "0000"

rx_data_r <= "00000000"

ELSIF (clk'EVENT AND clk = '1') THEN

IF (rx_int_xhdl0 = '1') THEN

IF (clk_bps = '1') THEN

num <= num + "0001"

CASE num IS

WHEN "0001" =>

rx_temp_data(0) <= rs232_rx

WHEN "0010" =>

rx_temp_data(1) <= rs232_rx

WHEN "0011" =>

rx_temp_data(2) <= rs232_rx

WHEN "0100" =>

rx_temp_data(3) <= rs232_rx

WHEN "0101" =>

rx_temp_data(4) <= rs232_rx

WHEN "0110" =>

rx_temp_data(5) <= rs232_rx

WHEN "0111" =>

rx_temp_data(6) <= rs232_rx

WHEN "1000" =>

rx_temp_data(7) <= rs232_rx

WHEN OTHERS =>

END CASE

ELSIF (num = "1100") THEN

num <= "0000"

rx_data_r <= rx_temp_data

END IF

END IF

END IF

END PROCESS

rx_data <= rx_data_r

END trans

如果需要转换verilog和vhdl可以使用x-hdl这个软件 添加文件之后点一下就行了 非常方便

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