when语句来实现，而对于外部输入的三个控制信号，也就相当于是一个计数器的控制信号，，你可以这样
entity
shuma
is
port(clk,reset:in
std_logic
start,cs:in
std_logic
disp1,disp2:out
std_logic_vector(7
downto
0)
led:out
std_logic)
end
entity
architecture
art
of
shuma
is
signal
count1:integer
range
0
to
......自已算
signal
count2,count3:integer
range
0
to
99
signal
clk_div,led_flag:std_logic
begin
process(clk,reset,count1)----首先进行时钟分频，分成1hz的；
begin
if
reset='1'
then
count1<=0
elsif
clk'段正和event
and
clk='1'
then
if
count1=??
then
---这个倍数根据你的fpga板的时钟频率和1hz进行计算
count1<=0clk_div<=not
clk_div
else
count<=count+1
end
if
end
if
end
process
process(clk_div,reset,count2)
---数码握盯管计数进程；
begin
if
reset='1'
then
count2<=0
elsif
clk_div'event
and
clk_div='1'
then
if
count2=99
then
led_flag<='1'--led亮的标志；
count2<=0
else
count2<=count2+1led_flag<='0'
end
if
end
if
end
process
process(count)--将计数的数值显示在数码管上,,用动态扫描法，对应关系
begin
自已查；
case
count
is
when
0=>disp1,disp2...
end
case
同样的led和测试程序
就是一个计数器，和上面类似，，，我要去上课啦，，希望以上那些可以帮助你！！！
library ieeeuse ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity led is
port(
clk:in std_logic--------------------------------时钟信号
s:out std_logic_vector(7 downto 0)--------------数码管
q:out std_logic_vector(6 downto 0))-------------段位
end led
architecture one of led is
signal clk1:std_logic
signal clk2:std_logic---------------分频肆笑
signal cnt:integer:=0
signal cnt1:integer:=0---------------计数
signal cnt2:integer:=0
signal count1:integer:=0
signal count2:integer:=0
signal data:integer range 0 to 9
begin
process(clk)
begin
if clk'event and clk = '1' then
if count1 = 49999999 then
clk1 <= '1'-------------------------------------1 s,以便好计算
count1 <= 0
else
count1 <= count1+1
clk1 <= '0'
end if
if count2 = 50000 then
clk2 <= '1'-------------------------------------1000hz，此闹雹燃液虚频率可利用人的视觉误差扫描数码管
count2 <= 0
else
count2 <= count2+1
clk2 <= '0'
end if
end if
end process
---VHDL源代码。 文件名： digital_clock.vhdlibrary ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity digital_clock is
port(
reset,clk: in std_logic
hour,minitue,second: out std_logic_vector(7 downto 0)
hex0,hex1,hex2,hex3,hex4,hex5: out std_logic_vector(6 downto 0))
end digital_clock
architecture one of digital_clock is
signal clk_count: std_logic_vector(22 downto 0)
signal clkm: std_logic
signal second1,second2: std_logic_vector(3 downto 0)
signal minitue1,minitue2: std_logic_vector(3 downto 0)
signal hour1,hour2: std_logic_vector(3 downto 0)
begin
hour(7 downto 0) <= hour2(3 downto 0) &hour1 (3 downto 0)
minitue(7 downto 0) <= minitue2(3 downto 0) &minitue1(3 downto 0)
second(7 downto 0) <= second2(3 downto 0) &second1(3 downto 0)
process(clk)
begin
if (clk'event and clk ='1') then
clk_count <颂者段= clk_count + 1
end if
end process
clkm <= clk_count(22)
------------------------
process(clkm)
begin
if(reset='1')then
hour2 <= "0000"hour1<嫌盯="0000"minitue2 <="0000"minitue1 <="0000"second2<="0000"second1<="0000"
elsif (clkm'event and clkm='1') then
if (hour2 = "0101" and hour1 ="1001" and minitue2 ="0101" and minitue1 ="1001" and second2 ="0101" and second1 ="1001")then
hour2 <= "0000"hour1 <= "0000"minitue2 <="0000"minitue1 <="0000"second2<="0000"second1<="0000"
elsif(hour1 ="1001" and minitue2 ="0101" and minitue1 ="1001" and second2 ="0101" and second1 ="1001")then
hour2 <= hour2 +1hour1 <= "0000"minitue2 <="0000"minitue1 <="0000"second2<="0000"second1<="0000"
elsif(minitue2 ="0101" and minitue1 ="1001" and second2 ="0101" and second1 ="1001")then
hour1 <= hour1 +1minitue2 <="0000"minitue1 <="0000"second2<="0000"second1<="0000"
elsif(minitue1 ="1001" and second2 ="0101" and second1 ="1001")then
minitue2 <=minitue2 +1minitue1 <="0000"second2<="野誉0000"second1<="0000"
elsif(second2 ="0101" and second1 ="1001")then
minitue1 <=minitue1 +1second2<="0000"second1<="0000"
elsif(second1 ="1001")then
second2 <= second2 +1second1 <= "0000"
else
second1 <= second1 +1
end if
end if
end process
------------------------
process(hour2,hour1,minitue2,minitue1,second2,second1)
begin
case second1(3 downto 0) is
when "0000" =>hex0(6 downto 0) <="1000000"
when "0001" =>hex0(6 downto 0) <="1111001"
when "0010" =>hex0(6 downto 0) <="0100100"
when "0011" =>hex0(6 downto 0) <="0110000"
when "0100" =>hex0(6 downto 0) <="0011001"
when "0101" =>hex0(6 downto 0) <="0010010"
when "0110" =>hex0(6 downto 0) <="0000010"
when "0111" =>hex0(6 downto 0) <="1111000"
when "1000" =>hex0(6 downto 0) <="0000000"
when "1001" =>hex0(6 downto 0) <="0010000"
when others =>hex0(6 downto 0) <="1000000"
end case
case second2(3 downto 0) is
when "0000" =>hex1(6 downto 0) <="1000000"
when "0001" =>hex1(6 downto 0) <="1111001"
when "0010" =>hex1(6 downto 0) <="0100100"
when "0011" =>hex1(6 downto 0) <="0110000"
when "0100" =>hex1(6 downto 0) <="0011001"
when "0101" =>hex1(6 downto 0) <="0010010"
when others =>hex1(6 downto 0) <="1000000"
end case
case minitue1(3 downto 0) is
when "0000" =>hex2(6 downto 0) <="1000000"
when "0001" =>hex2(6 downto 0) <="1111001"
when "0010" =>hex2(6 downto 0) <="0100100"
when "0011" =>hex2(6 downto 0) <="0110000"
when "0100" =>hex2(6 downto 0) <="0011001"
when "0101" =>hex2(6 downto 0) <="0010010"
when "0110" =>hex2(6 downto 0) <="0000010"
when "0111" =>hex2(6 downto 0) <="1111000"
when "1000" =>hex2(6 downto 0) <="0000000"
when "1001" =>hex2(6 downto 0) <="0010000"
when others =>hex2(6 downto 0) <="1000000"
end case
case minitue2(3 downto 0) is
when "0000" =>hex3(6 downto 0) <="1000000"
when "0001" =>hex3(6 downto 0) <="1111001"
when "0010" =>hex3(6 downto 0) <="0100100"
when "0011" =>hex3(6 downto 0) <="0110000"
when "0100" =>hex3(6 downto 0) <="0011001"
when "0101" =>hex3(6 downto 0) <="0010010"
when others =>hex3(6 downto 0) <="1000000"
end case
case hour1(3 downto 0) is
when "0000" =>hex4(6 downto 0) <="1000000"
when "0001" =>hex4(6 downto 0) <="1111001"
when "0010" =>hex4(6 downto 0) <="0100100"
when "0011" =>hex4(6 downto 0) <="0110000"
when "0100" =>hex4(6 downto 0) <="0011001"
when "0101" =>hex4(6 downto 0) <="0010010"
when "0110" =>hex4(6 downto 0) <="0000010"
when "0111" =>hex4(6 downto 0) <="1111000"
when "1000" =>hex4(6 downto 0) <="0000000"
when "1001" =>hex4(6 downto 0) <="0010000"
when others =>hex4(6 downto 0) <="1000000"
end case
case hour2(3 downto 0) is
when "0000" =>hex5(6 downto 0) <="1000000"
when "0001" =>hex5(6 downto 0) <="1111001"
when "0010" =>hex5(6 downto 0) <="0100100"
when "0011" =>hex5(6 downto 0) <="0110000"
when "0100" =>hex5(6 downto 0) <="0011001"
when "0101" =>hex5(6 downto 0) <="0010010"
when others =>hex5(6 downto 0) <="1000000"
end case
end process
end one
－－－－－在DE2板上验证 时钟频率有点高，可以在clk_count中增加位数作调整
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