如何用VHDL语言编写两个输入与门两个或门

与门和丛友或或门之间是什么关系？

如果输入相同的渗伍话，用“C<=A AND B；”可以描述两输入端与门，用“D<=A OR B；”可以描述两输入端或门。将这两个并行告吵语句在结构体中描述即可，无所谓描述顺序。

给你看个例化的例子：三输入 或门例化2输入或门

library ieee

use ieee.std_logic_1164.all ---2输入或门

entity huo is

port(a,b:in std_logic

c:out std_logic)

end entity

architecture art of huo is

begin

c<=a or b

end art

library ieee

use ieee.std_logic_1164.all

entity huo_3 is 3输入或门

port(a,b,c:in std_logic

d:out std_logic)

end entity

architecture art of huo_3 is

component huo is --对应将2输凯消皮入或门的实体桥态写进去，port里面一个字母都不能差

port(a,b:in std_logic

c:out std_logic)

end component

signal ab:std_logic

begin

u1:huo port map(a=>a,b=>b,ab=>c)--对应将两个模块的端口连接起来，

u2:huo port map(ab=>盯差a,c=>b,c=>d)

end art

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

ENTITY GATE IS

PORT(A,B:IN STD_LOGIC

YAND,YOR,YXOR,YNOT:OUT STD_LOGIC)

END GATE

ARCHITECTURE ART OF GATE IS

BEGIN

YAND<=A AND B

YOR<=A OR B

YXOR<=A XOR B

YNOT<=A NOT B

END ART

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