写了个verilog流水灯程序，quartus一直提示子模块重复定义。

这是你交橘察叉`include出现的问题

推荐你在divd.v

开头写上

`ifndef DIVD_V

`define DIVD_V

在最后写上

`endif

这样只要文件之前被include过兄伍脊了，就会有DVID_V这个define，这样就能避免羡渗同一个文件在不同的地方被include造成的重复declare

Vivado Logic Analyzer的使用 chipscope中，通常有两种陪喊方法设置需要捕获的信号。 1.添加cdc文件，然后在网表中寻找并正乱姿添加信号 2.添加ICON、ILA和VIO的IP Core 第一种方法，代码的修改量小，适当的保留设计的层级和网举绝线名，图形化界面便于找到 需

AR# 53028

2012.x Vivado - "ERROR: [Common 17-39] 'launch_xsim' failed due to earlier errors"

Description

Solution

Linked Answer Records

Description

I have a design in the Vivado tool which I want to run a behavioral simulation with different parameters. For this task, I have created some simulation runs with different names as follows:

"sim1 model_PCIe"

"sim2"

"sim3(model_GTX)"

However, when I attempt to run the simulation, the following error appears:

"ERROR: [Common 17-39] 'launch_xsim' failed due to earlier errors"

Why does this occur?

Solution

This is a known issue that occurs in Vivado when a simulation run that contains blank or empty spaces in the name is executed.

In this case, for the run "sim1 model_PCIe"慧族

To avoid this problem, remove the spaces as follows: "前晌弊谨斗sim1_model_PCIe".

This issue is fixed in the Vivado 2013.1 tool.

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