用ALU实现的4位累加器，用verilog语言来完成

将always模块改仿穗成下面的试试备猛卜看

always @(posedge clk or posedge rst)

begin

if(rst) begin

areg<知岁=0

end

else begin

areg<=areg+y

end

end

library ieee

use ieee.std_logic_1164.all

use ieee.std_logic_signed.all

entity alu is

port (a,b:in std_logic_vector(3 downto 0)

c, d , e, f: out std_logic_vector(3 downto 0))

end alu

architecture behav of alu is

begin

c <= a + b

d <= a - b

e <镇脊穗= a and b

f <= a or b

end behav

备注御卜：Quartus II 8.0下 编译及仿野谈真通过。

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